Interleaved Folded Current-Steering DAC for High-Speed Low-Power Output

The patent divides the current steering DAC system into multiple parallel sub-DACs (e.g., two or more interleaved sub-DACs). Each sub-DAC operates at a lower individual sampling frequency, allowing them to consume less power and operate below the dielectric breakdown threshold, while collectively achieving high-speed operation through interleaving. This segmentation resolves the contradiction by distributing the high-speed operation burden across multiple lower-power units.

The patent employs periodic switching between multiple interleaved sub-DACs, where each sub-DAC is activated in alternating time slots or phases. This periodic activation allows each sub-DAC to operate intermittently at lower power levels while maintaining an effective high sampling frequency at the system level, thus resolving the power consumption versus speed contradiction.

By segmenting the high-speed operation across multiple interleaved sub-DACs, each operating at reduced individual speeds, the patent ensures that no single sub-DAC experiences the high electric field stress and rapid switching that cause time-dependent dielectric breakdown. This segmentation protects reliability while achieving high system-level sampling frequency.

The patent designs the interleaved architecture with built-in redundancy and load distribution, cushioning each sub-DAC from excessive stress. By预先 distributing the operational load and avoiding concentration of high-speed switching in a single unit, the system preemptively reduces the risk of dielectric breakdown before it can occur.