Interleaved DAC Clock Phase Alignment for High Sampling Rates
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Solution Overview
Problem
Modern CMOS-based digital signal processor ASICs face challenges in achieving high sampling rates for digital-to-analog converters (DACs) due to phase mismatches caused by voltage, temperature, and process variations in time-interleaved architectures, leading to performance degradation.
Innovation Solution
The implementation of a phase detector and delay locked loop circuit for clock phase alignment in N-time interleaved DACs, using a current domain XOR-based phase detector and voltage-to-current converters to align FS/2 and FS/4 clocks, ensuring accurate timing and minimizing errors across various conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved DAC architecture is used to increase sampling rate, then productivity is improved, but reliability deteriorates due to phase mismatches from voltage, temperature, and process variations
Solution Approach 1:
The patent implements a feedback mechanism using a phase detector that continuously monitors the phase difference between clocks from different DACs and adjusts their timing alignment accordingly. This closed-loop feedback system compensates for phase mismatches caused by voltage, temperature, and process variations, maintaining reliable operation while enabling high sampling rates through time-interleaved architecture
Solution Approach 2:
The patent dynamically adjusts clock phase parameters in response to changing operating conditions. By detecting phase mismatches and modifying clock timing parameters in real-time, the system maintains accurate synchronization across multiple DACs despite variations in voltage, temperature, and manufacturing processes
2Productivity
If multiple DACs are used in time-interleaved configuration, then productivity is improved, but device complexity increases due to additional clock distribution and synchronization requirements
Solution Approach 1:
The patent introduces a phase detector as an intermediary component that mediates between multiple DAC clock sources. This intermediary device detects phase differences and enables automatic timing alignment, simplifying the overall clock distribution system while supporting high sampling rates through time-interleaved configuration
Data Source
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AI summary
Described herein are apparatus and methods for realization of time interleaved digital-to-analog converters (DACs) by detecting and aligning phase mismatches. In an implementation, a N-time interleaved DAC includes N DACs and N replica DACs, where a first set of N/2 DACs operate at a clock A and a second set of N/2 DACs operate at a clock B, and where N is at least two. The phase detector generates a phase detection output by comparing outputs of the first and second set of N/2 replica DACs with a multiplexor (MUX) clock, where the MUX clock is a multiple of a frequency of the clock A or the clock B. The clock A and the clock B are aligned with the MUX clock by advancing a phase of the clock A and the clock B until the phase detection output achieves a zero crossing.