Interleaved DAC Calibration for Duty-Cycle and Phase Error Correction
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Solution Overview
Problem
Interleaved digital-to-analog converters (DACs) face performance degradation due to dynamic errors such as timing errors and duty-cycle mismatch, especially at ultra-high clock rates, which are challenging to address and impact spectral purity and Spurious Free Dynamic Range (SFDR).
Innovation Solution
A calibration method using a low-frequency loop with a low-speed analog-to-digital converter (ADC) and digital signal processor (DSP) to detect and calibrate duty-cycle and phase errors, enabling scalable duty cycle and phase calibration in multi-gigabit per second DACs, effectively minimizing spurious signals and improving spectral performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interleaved DAC operates at ultra-high clock rates to achieve high conversion rates, then productivity is improved, but timing errors and duty-cycle mismatch increase causing spectral purity degradation
Solution Approach 1:
The patent applies preliminary action by performing calibration of duty cycle and phase relationships before the interleaved DAC operates at ultra-high clock rates. The calibration process adjusts timing parameters in advance to compensate for expected timing errors and duty-cycle mismatch that would otherwise occur during high-speed operation, thereby maintaining spectral purity while achieving high conversion rates
Solution Approach 2:
The patent implements feedback through a calibration mechanism that measures timing errors and duty-cycle mismatch during operation and uses this information to adjust clock phase relationships. The system continuously monitors spectral purity metrics and feeds this information back to the calibration logic, which then modifies timing parameters to minimize timing errors and maintain high spectral purity at ultra-high clock rates
2Manufacturing precision
If foreground calibration loops and Dynamic Element Matching are used to fix static errors, then manufacturing precision is improved, but timing errors remain difficult to address
Solution Approach 1:
The patent applies segmentation by separating the calibration process into distinct stages: one stage handles static errors through traditional foreground calibration loops and Dynamic Element Matching, while a separate stage specifically addresses timing errors through phase relationship calibration. This segmentation allows each calibration mechanism to be optimized independently, reducing overall device complexity while comprehensively addressing both static and dynamic errors
Solution Approach 2:
The patent introduces an intermediary calibration mechanism that acts as a mediator between the static error correction processes and timing error compensation. This intermediary phase calibration process translates and coordinates the calibration of clock phases and duty cycles, enabling timing error correction to work effectively alongside existing static error correction mechanisms without significantly increasing overall device complexity
3Measurement precision
If feedback loop detects and compensates for clock skew and timing errors at multi-Gbps operation, then spectral purity is improved, but the complexity of realizing femtosecond-level precision increases significantly
Solution Approach 1:
The patent applies parameter changes by focusing the feedback loop on calibrating specific critical parameters (clock phase relationships and duty cycles) rather than attempting to control all timing parameters simultaneously. By identifying and adjusting only the most influential parameters that affect spectral purity at femtosecond levels, the system achieves high precision while keeping the calibration system complexity manageable
Solution Approach 2:
The patent implements local quality by applying different calibration strategies to different parts of the interleaved DAC system. Critical sub-DACs with larger timing errors receive more aggressive calibration attention, while others use standard calibration. The calibration intensity and methodology are locally adapted based on the specific timing error characteristics of each sub-DAC group, reducing overall system complexity while maintaining femtosecond-level spectral purity
4Measurement precision
If careful design and area consuming layout techniques are used to address timing errors, then spectral purity is improved, but device area increases
Solution Approach 1:
The patent applies self-service by implementing calibration logic that automatically detects and corrects timing errors and duty-cycle mismatch without requiring extensive manual layout adjustments or additional calibration hardware. The interleaved DAC system includes built-in calibration circuits that self-adjust timing parameters during operation, eliminating the need for area-consuming layout techniques while maintaining high spectral purity
Data Source
AI summary
A system and method are provided for calibrating an interleaved digital-to-analog converter (DAC). Sets of sub-DACs are enabled, and by creating a high frequency fundamental signal, spurs can be driven down sufficiently low in frequency to be sampled and digitally converted. By minimizing the power of these digital signals, the duty cycles of the different clock phases are calibrated. Then, sets of sub-DACs are enabled and high pass filtered, so that the spurs can be downconverted using corresponding phases of the clock, to a frequency low enough to sampled and digitally converted. The power of the digital signals is minimized as a first step in phase calibration. As a final step, all the sub-DACs are enabled, the high pass filter removed, and a high frequency fundamental signal is downconverted using at least two clock phases, so that the phase difference can be measured and corrected.