Interleaved DAC Signal Generator for Stable Multi-Channel Phase Control
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Solution Overview
Problem
Conventional signal generators experience unstable synchronization between channels at high clock speeds, making it difficult to generate stable and synchronized output signals with user-defined phase differences, especially as electronic device operating speeds increase beyond 100 MHz.
Innovation Solution
The signal generator employs clock phase shifters to provide continuous clocks to signal generation blocks, allowing for phase control and synchronization, enabling the generation of signals with multiple levels in one clock cycle, thereby achieving higher time resolution than the clock speed. This is achieved through phase comparators, controllers, and digital-to-analog converters that manage phase relationships and duty cycles to ensure non-overlapping data bits and reference levels in combined output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock speed is increased to generate faster signal outputs, then productivity is improved, but stability of channel synchronization deteriorates
Solution Approach 1:
The patent divides the single high-speed clock function into multiple interleaved DAC channels, each operating at a lower individual clock speed but collectively achieving high output throughput. Each DAC channel processes alternating samples (even/odd) at reduced clock rates, maintaining synchronization stability while achieving overall high productivity through parallel channel operation.
2Adaptability or versatility
If multiple signal channels are added to provide multiple stimulation signals, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple DAC channels into a single integrated signal generator device with shared control logic and interleaved operation. Multiple signal channels are generated through parallel DAC units that share common waveform memory and control resources, reducing overall device complexity while maintaining adaptability for multiple stimulation signals.
3Adaptability or versatility
If phase control is implemented to provide user-defined phase differences, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service phase control where the interleaved DAC structure automatically provides precise phase relationships through its inherent time-interleaved operation. The phase differences between channels are naturally determined by the sampling interval and DAC conversion timing, eliminating the need for additional external phase shifters or complex phase control circuitry.
Data Source
AI summary
A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.