Time-Interleaved Current-Steering DAC With Reset-Load Switching

The patent divides the high-speed DAC into multiple parallel sub-DACs operating at lower speeds. Each sub-DAC processes a portion of the data stream, allowing individual settling times to be met while achieving high overall bandwidth through parallel operation. This segmentation resolves the contradiction by enabling fast aggregate conversion without requiring each component to operate at the full high speed.

The patent employs time-interleaved periodic switching between multiple sub-DACs, where each sub-DAC is activated in alternating time slots. This periodic activation allows each sub-DAC to settle completely before its next activation, ensuring precise timing and settling requirements are met while maintaining high overall conversion speed through the periodic contribution of multiple units.

The patent merges the outputs of multiple sub-DACs through a combining network that aligns their contributions in the time domain. By carefully designing the combining architecture and using calibration techniques, the patent eliminates timing skew between sub-DACs and ensures their outputs are properly synchronized, thereby maintaining high timing accuracy while benefiting from the reduced power consumption of distributed operation.

The patent implements calibration and correction mechanisms that use feedback from timing error detection to adjust the operation of individual sub-DACs. This feedback system measures actual timing skew and settling errors, then applies compensating adjustments to maintain precise timing accuracy despite the distributed architecture, while preserving the power efficiency gains from using multiple lower-speed units.