Interleaved Return-to-Zero DAC for Low-Distortion Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital-to-analog converters (DACs) face challenges with non-linearities during transistor switching, leading to distortion in high-speed applications, with Class A DACs consuming high power and Class B DACs being unsuitable for high performance due to power savings at the cost of distortion.
Innovation Solution
An interleaved, return-to-zero (IRZ) high performance DAC design using two banks of current cells, where one bank is alternately activated while the other is nearly off, mitigating distortion and reducing power consumption by employing an interleaved return-to-zero technique.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Class A DAC architecture is used, then high-speed characteristics and signal power are maintained, but power consumption increases
Solution Approach 1:
The current source array is divided into two separate banks (Bank A and Bank B), each handling alternating clock cycles. This segmentation allows one bank to be fully active while the other is inactive, reducing overall power consumption while maintaining high-speed performance during active periods.
Solution Approach 2:
The DAC employs periodic switching between Bank A and Bank B based on clock cycles. Each bank is activated alternately, with Bank A active during even clock cycles and Bank B active during odd clock cycles. This periodic action reduces average power consumption while maintaining high-speed characteristics during active periods.
2Use of energy by moving object
If Class B DAC architecture is used, then power consumption is reduced, but distortion increases due to non-linearities during transistor switching
Solution Approach 1:
Current is pre-charged to the output node during the inactive period of each bank before switching occurs. This preliminary charging action ensures that when the active bank switches on, the output node already has the appropriate voltage level, minimizing transient distortion and non-linearities during the switching transition.
Solution Approach 2:
The patent introduces intermediate charging circuits and precharge switches that act as mediators between the current sources and the output node. These intermediaries prepare the output node in advance and smooth the transition during bank switching, reducing distortion while maintaining power efficiency.
3Use of energy by moving object
If interleaved return-to-zero technique is used, then power consumption is reduced and distortion is mitigated, but device complexity increases
Solution Approach 1:
The patent merges the functionality of two banks into a single unified current source array structure. Both banks share common output nodes and control logic, and the switching between banks is managed through integrated control circuits. This merging approach reduces the overall device complexity compared to having completely separate DAC structures while still achieving power reduction and distortion mitigation.
Data Source
AI summary
In one method embodiment, receiving a data signal; and converting the data signal to an analog signal over plural clock cycles, the converting comprising: during a first clock cycle of the plural clock cycles, switching on one or more first current cells of a first bank while simultaneously a second bank comprising second current cells is switched off or almost off; and during a second clock cycle of the plural clock cycles, the second clock cycle immediately subsequent to the first clock cycle, switching on one or more of the second current cells of the second bank while simultaneously the first bank is switched off or almost off.