Interleaved DAC Architecture Without Return-to-Zero Limits
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Solution Overview
Problem
Developing high-speed, high-precision digital-to-analog converters (DACs) for high-frequency systems, such as 112 GHz, is challenging due to fundamental limitations in traditional DAC architectures, particularly the return-to-zero technique which restricts the pulse width of clock signals, making it difficult to scale up conversion speeds.
Innovation Solution
An interleaved DAC architecture using N positive sub-DACs and N−1 negative sub-DACs, where each positive sub-DAC operates for N×T and each negative sub-DAC for (N−1)×T, with aligned rising edges and phase-offset clock signals, allowing simultaneous operation and overlap of sub-DACs to achieve the desired data conversion speed without return-to-zero limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If return-to-zero technique is used in interleaved DAC, then each sub-DAC can operate independently with non-overlapping clock pulses, but the pulse width is restricted to T=1/fs making it difficult to achieve high conversion speeds
Solution Approach 1:
The invention divides the high-speed DAC operation into multiple parallel sub-DACs, each operating at lower speed. The input data stream is segmented into multiple channels that are processed simultaneously by different sub-DACs with phase-offset clock signals, enabling the overall system to achieve high conversion speed while each individual sub-DAC operates within feasible speed limits.
Solution Approach 2:
The invention applies preliminary dithering to the input data before it enters the sub-DACs. This preliminary action of adding dither noise prepares the signal in advance to prevent correlation errors that would otherwise occur due to the non-return-to-zero nature of the clock signals, enabling extended pulse widths without compromising signal integrity.
2Productivity
If multiple interleaved sub-DACs are used to scale up conversion speed, then the overall data conversion rate increases, but the pulse width for each sub-DAC becomes narrower making implementation more difficult
Solution Approach 1:
The invention introduces dynamic dithering that varies over time and across different sub-DAC channels. This dynamic adjustment of dither parameters allows the system to optimize performance for each sub-DAC's specific operating conditions, making it easier to implement sub-DACs with extended pulse widths while maintaining high overall conversion rates.
Solution Approach 2:
The invention changes the dither parameters (amplitude, frequency, distribution) to optimize the operation of multiple interleaved sub-DACs. By adjusting these parameters, the system can accommodate the extended pulse widths required for easier sub-DAC implementation while maintaining the high overall data conversion rate through coordinated operation of multiple channels.
3Ease of manufacture
If clock pulse width is extended beyond T=1/fs for easier sub-DAC implementation, then manufacturing becomes easier, but sub-DAC outputs may overlap causing correlation errors
Solution Approach 1:
The invention applies dithering as a preliminary action to the input signal before it is processed by the sub-DACs. This pre-processing step modifies the signal characteristics in advance to prevent correlation errors that would arise from overlapping sub-DAC outputs, thereby allowing extended pulse widths without compromising signal accuracy.
Solution Approach 2:
The dither signal acts as an intermediary between the overlapping sub-DAC outputs and the final reconstructed signal. By introducing this intermediate dither component, the system can tolerate overlapping outputs from sub-DACs with extended pulse widths while maintaining overall signal integrity and preventing correlation errors in the final output.
Data Source
AI summary
An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N−1)/fs, and by a delay of 1/fs. The positive sub-DAC and the negative sub-DAC start the conversion at the same time. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.