Interleaved Data Streams on Common Port
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Solution Overview
Problem
Conventional data communication methods require additional pins and circuit board conductors to handle multiple data streams, which increases circuit board area and parasitic inductance, and are not compatible with legacy components when using interleaved data streams at higher rates.
Innovation Solution
A system where multiple data streams are interleaved and presented on a common data bus with phase-shifted clock signals, allowing destinations to receive data streams at a conventional clock rate, compatible with existing standards, without the need for additional pins or conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate data buses and clock signals are used for multiple data streams, then data communication reliability is improved, but device complexity and circuit board area increase
Solution Approach 1:
The patent combines multiple data streams onto a single shared data bus, eliminating the need for separate data buses for each stream. Multiple clock signals are also multiplexed onto a single clock bus. This merging approach reduces the number of required conductors and pins while maintaining reliable synchronous communication through proper timing control and data stream identification protocols.
Solution Approach 2:
The shared data bus and clock bus are designed to handle multiple data streams simultaneously, making them multi-functional resources. The system uses universal bus structures that can carry different data streams at different times or in interleaved fashion, reducing hardware requirements while maintaining communication reliability for multiple streams.
2Productivity
If additional pins and conductors are added to handle multiple data streams, then data communication capacity is improved, but parasitic inductance increases
Solution Approach 1:
By merging multiple data streams onto a single shared data bus and multiple clock signals onto a single clock bus, the patent reduces the total number of conductors required. This consolidation directly reduces the cumulative parasitic inductance that would otherwise be present in multiple separate bus structures, while still maintaining the capacity to communicate multiple data streams through time-division or interleaved techniques.
3Productivity
If interleaved data streams are transmitted at higher rates, then productivity is improved, but compatibility with legacy components deteriorates
Solution Approach 1:
The patent employs periodic time-division multiplexing where different data streams are transmitted in alternating time slots or periods on the shared bus. This periodic structure allows legacy components to synchronize with the clock signal and process data at their native rates while the overall system achieves higher throughput through the interleaved transmission of multiple streams. The periodic nature maintains timing coherence for legacy devices.
Solution Approach 2:
The high-rate data stream is segmented into discrete time slots or packets, each belonging to a different source stream. Legacy components can process these segmented data units at their original lower rates while the system achieves higher aggregate productivity through parallel transmission of multiple segmented streams over the shared bus infrastructure.
Data Source
AI summary
A video display system, such as useful in video surveillance applications, is disclosed. The system includes a video decoder (20) having a common output data port (27) at which it presents interleaved data streams (DSA, DSB). The interleaved data streams (DSA, DSB) may correspond to multiple scalings of a processed video input signal, for example as received from a surveillance camera (C1, C2, C3, C4). The video decoder (20) also outputs multiple clock signals (CLKA, CLKB), each of which are synchronous with a corresponding one of the interleaved data streams (DSA, DSB). This enables a common data port (27) to output multiple data streams (DSA, DSB), while individual destinations (30A, 30B) of the data streams (DSA, DSB) can continue to operate at legacy clock rates.