Interleaved DC Interconnects for Parasitic Inductance Reduction
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Solution Overview
Problem
Electrical parasitic elements in DC interconnections with switching circuitry lead to voltage ringing and transient effects, which can be damaging and compromise operations, and existing solutions either increase costs or compromise performance.
Innovation Solution
The implementation of interleaved electrical interconnections between substrates or circuit boards, utilizing capacitors and voltage rails to reduce parasitic inductance, thereby minimizing voltage ringing and transient effects without adding components or modifying switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional DC interconnections are used with switching circuitry, then the circuit layout is simple, but parasitic inductance causes voltage ringing and transient effects
Solution Approach 1:
The connection interfaces are divided into multiple subsets (first subset connected to first reference voltage node, second subset connected to second reference voltage node) that are interleaved with each other. This segmentation of the interconnection structure reduces the loop area for each individual connection, thereby reducing parasitic inductance and voltage ringing without adding external components.
Solution Approach 2:
The patent transitions from a conventional linear or block-based connection layout to an interleaved spatial arrangement where connection interfaces from different voltage references are alternated. This dimensional reorganization of the connection pattern minimizes the physical distance and loop area between opposing polarity connections, reducing parasitic inductance while maintaining a compact single-substrate structure.
2Object-affected harmful factors
If snubber circuits are added to mitigate voltage transients, then voltage ringing is reduced, but system cost and complexity increase
Solution Approach 1:
The patent extracts the voltage transient mitigation function from external snubber circuits and integrates it directly into the DC interconnection structure itself. By designing the connection interfaces to be interleaved and minimizing loop area at the structural level, the system achieves voltage transient reduction without requiring separate snubber components, thereby reducing overall system complexity and cost.
Solution Approach 2:
The DC interconnection structure provides its own protection against voltage transients through its inherent interleaved geometry. The structure serves its primary function of electrical connection while simultaneously providing parasitic inductance reduction, eliminating the need for separate protective components and making the system self-sufficient.
3Object-affected harmful factors
If soft turn off switching operations are used, then voltage transients are reduced, but system performance and efficiency are compromised
Solution Approach 1:
The patent implements preliminary action by designing the interconnection structure to have minimal parasitic inductance before switching events occur. The interleaved connection pattern is built into the substrate layout in advance, so that when switching operations occur, the reduced loop area inherently limits voltage transients without requiring modification of the switching waveform or soft turn-off techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic inductance, mitigates voltage ringing, and improves thermal isolation, allowing for more efficient and stable DC voltage management in electrical systems.
Implementation Method 1
one or more capacitive elements coupled between the pair of voltage rails to provide a direct current (DC) link capacitance
Implementation Method 2
A first subset of the first plurality of connection interfaces is electrically connected to a first reference voltage node, a second subset of the first plurality of connection interfaces is electrically connected to a second reference voltage node different from the first reference voltage node, and the first subset and the second subset are interleaved with one another
Data Source
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AI summary
Electrical systems and devices with substrate interconnections having reduced parasitic inductance are provided. A first substrate includes one or more capacitors and plurality of connection interfaces, wherein a first subset of connection interfaces electrically connected to a first reference voltage are interleaved with a second subset of connection interfaces electrically connected to a different reference voltage. A second substrate includes a third subset of connection interfaces are electrically connected to a first terminal of a first switching element and the first subset of connection interfaces and a fourth subset of connection interfaces electrically connected to a second terminal of a second switching element and the second subset of connection interfaces, and the third subset and the fourth subset are also interleaved.