Interleaved Decoder Erasure Signaling for Low-Memory Error Correction
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Solution Overview
Problem
Existing data communication systems over noisy signal transmission paths, such as DSL, face challenges in effectively decoding signals due to impulse noise and radio frequency interference, particularly in correcting errors without increasing memory requirements or latency.
Innovation Solution
A decoder system that includes a first decoder unit for decoding a second level of encoding, a de-interleaving unit, and an identifier unit that provides error indication signals to a redundancy decoder, allowing for erasure decoding and reducing memory requirements by eliminating the need for a second de-interleaver unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional decoding systems use redundancy encoding and interleaving to correct errors, then error correction capability is improved, but memory requirements and system complexity increase
Solution Approach 1:
The patent extracts and processes error indications from the first decoder unit before passing data to the de-interleaver. By identifying error locations early in the decoding chain and using this information to guide the redundancy decoder, the system avoids needing to store and process entire interleaved blocks, thereby reducing memory requirements while maintaining error correction capability
Solution Approach 2:
The system performs preliminary error detection and indication extraction in the first decoder unit before the de-interleaving operation. This preliminary action allows the redundancy decoder to focus computational resources only on correcting identified errors rather than processing entire data blocks, reducing both memory and computational complexity
2Reliability
If redundancy encoding with parity bits is used to protect against noise, then reliability is improved, but data transmission rate decreases
Solution Approach 1:
The patent applies partial redundancy by using error indication signals to identify only the specific bytes that require correction. Instead of uniformly processing all parity bits for all data bytes, the system focuses correction efforts only on identified error locations, effectively using less redundancy processing to achieve the same reliability goal, thereby improving transmission efficiency
3Reliability
If interleaving is used to distribute impulse noise, then error distribution is improved, but decoding latency increases
Solution Approach 1:
The patent extracts error indication information from the first decoder unit before de-interleaving operations. By having the identifier unit process and forward error indications immediately, the system avoids the need to wait for complete de-interleaving of large data blocks before error correction can begin, thereby reducing decoding latency while maintaining the noise-distributing benefits of interleaving
Data Source
AI summary
Systems and methods for processing data signals are described. In one implementation, a demodulator and a first decoder unit, such as a convolutional encoder or a quadrature amplitude modulation decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal are provided. The decoded signal may be passed through a de-interleaving unit to form a de-interleaved signal. The first location signal may be passed to an identifier unit which receives it, and from it produces a second error indication signal indicative of the errors in the de-interleaved signal. The de-interleaved signal and the second error indication signal may be transmitted to a redundancy decoder, where the signals may be used to perform redundancy decoding.