Interleaved Delay Line Clock Paths for Glitch-Free Code Updates
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Solution Overview
Problem
Existing methods for updating delay line codes in memory interfaces introduce glitches in the clock strobe signal, leading to false strobe clock edges and data corruption, and require complex clock gating and sequencing operations, which increase area, power consumption, and reduce system bandwidth.
Innovation Solution
A method and circuit for dynamically updating delay line codes using a coarse delay line with interleaved logic gates, generating two clock paths (C_EVEN and C_ODD) and a fine delay cell, allowing for on-the-fly switching without glitches by determining dependency on either clock path and adjusting the number of logic gates to maintain delay alignment, thereby eliminating the need for elaborate clock gating and sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay line code is updated using existing methods, then delay alignment can be adjusted, but glitches are introduced in the clock strobe signal causing false edges and data corruption
Solution Approach 1:
The delay line is segmented into multiple independent delay cells, each controllable by separate clock paths. This segmentation allows individual cells to be updated without affecting the entire delay line, enabling glitch-free code updates by isolating transitions to non-overlapping time periods.
Solution Approach 2:
The update mechanism uses periodic clock gating where clock paths are enabled and disabled in alternating periods. By updating delay line codes during disabled periods and using complementary clock phases, the system ensures that code changes occur without propagating to the output during active periods, preventing glitches while maintaining continuous operation.
2Ease of operation
If complex clock gating and sequencing operations are used to update delay line codes, then update control can be achieved, but device complexity and area increase
Solution Approach 1:
The delay line cells are designed to automatically respond to clock enable signals without requiring external control logic. Each delay cell contains internal gating that activates based on its assigned clock phase, eliminating the need for complex external sequencing circuits and reducing overall system complexity.
Solution Approach 2:
The clock gating mechanism serves multiple functions simultaneously: it enables selective updating of delay cells, provides glitch-free transitions, and maintains continuous clocking for active cells. This multi-functionality eliminates the need for separate control circuits for each update operation, reducing device complexity.
3Ease of operation
If elaborate clock gating and sequencing circuits are implemented, then update sequencing can be controlled, but power consumption increases
Solution Approach 1:
Clock paths are activated periodically rather than continuously, with each delay cell receiving clock signals only during its designated update window. This periodic activation ensures that power-consuming logic gates are active only when necessary for updates, significantly reducing overall power consumption while maintaining full update control capability.
Solution Approach 2:
The clock gating configuration is dynamically adjusted based on which delay cells require updating. The system activates only the minimum necessary clock paths for current update operations, adapting power consumption to actual operational needs rather than maintaining fixed high-power operation for all possible update scenarios.
4Adaptability or versatility
If delay line code updates are performed during operation, then dynamic adaptation is achieved, but system bandwidth is reduced due to update operations
Solution Approach 1:
The update operations are scheduled during periodic windows when specific clock paths are disabled, allowing code changes without interrupting data transmission on active paths. This periodic update strategy enables dynamic adaptation while maintaining continuous operational bandwidth during active periods.
Solution Approach 2:
Delay line code updates are prepared and staged during inactive periods before being applied to the active delay line. By performing preliminary configuration during clock-disabled windows and then enabling updated cells, the system achieves dynamic adaptation without interrupting ongoing data transmission, preserving system bandwidth.
Data Source
AI summary
The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.