Interleaved ECC Chip Correct and Fault Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Error Correction Code (ECC) algorithms in computer memory systems are limited in correcting multi-bit errors and providing fault isolation, as they operate with a word size less than or equal to the smallest critical word length, which is inadequate for high-end systems.
Innovation Solution
Implementing a wide ECC word over a collection of narrower data chunks with interleaving and data alignment, allowing for advanced chip correct functionality and finer fault isolation granularity, thereby enhancing the reliability and availability of computer memory systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC algorithms use word size less than or equal to the smallest critical word length, then the system operates with simpler error correction, but the correction capability and fault isolation granularity are insufficient
Solution Approach 1:
The patent divides the wide ECC word into multiple narrower data chunks (e.g., 256-bit ECC word divided into four 64-bit chunks). Each chunk is processed independently through the ECC algorithm, allowing the system to achieve multi-bit error correction capability while using simpler narrow-word ECC algorithms. This segmentation resolves the contradiction by enabling advanced correction capability without requiring a single complex wide-word ECC implementation.
Solution Approach 2:
The patent introduces an additional dimension of processing by implementing interleaving across multiple data chunks. Instead of processing a single wide word, the system processes multiple narrow words in parallel with interleaved error correction, effectively transforming the problem from one-dimensional wide-word correction to multi-dimensional narrow-word correction. This approach achieves enhanced correction capability while maintaining algorithm simplicity.
2Measurement precision
If conventional ECC algorithms operate with narrow word size, then the algorithm implementation is simpler, but the fault isolation granularity is too coarse to identify specific failed memory modules
Solution Approach 1:
By segmenting the memory data into multiple narrower chunks (e.g., 64-bit chunks from a 256-bit word), the patent enables finer fault isolation granularity. Each chunk can be independently analyzed to identify which specific memory module or chip has failed. The segmentation allows precise localization of errors to specific chunks, improving measurement precision for fault isolation.
Solution Approach 2:
The patent applies partial action by processing each data chunk independently through the ECC algorithm rather than treating the entire wide word as a single unit. This partial processing approach allows the system to achieve fine-grained fault isolation by examining each chunk separately, while still maintaining efficient throughput through parallel processing of multiple chunks.
3Reliability
If the system implements advanced chip correct functionality with wide ECC words, then multi-bit error correction is enabled, but the system complexity and implementation difficulty increase
Solution Approach 1:
The patent segments the wide ECC word into multiple narrower data chunks that can be processed using standard, well-understood narrow-word ECC algorithms. This segmentation approach enables multi-bit error correction capability while avoiding the need to implement complex wide-word ECC logic, thereby reducing manufacturing complexity and implementation difficulty. Each chunk can be handled by existing proven ECC designs.
Solution Approach 2:
The patent introduces an intermediary processing layer that handles the interleaving and de-interleaving of data chunks. This intermediary mechanism allows the system to achieve advanced chip correct functionality by coordinating multiple independent narrow-word ECC operations, rather than requiring a single complex wide-word ECC implementation. The intermediary layer simplifies the overall implementation by breaking down the complex task into manageable independent operations.
Data Source
AI summary
Systems and methods for implementing chip correct and fault isolation in computer memory systems are disclosed. An exemplary method may include interleaving check bits with a data word to form at least one interleaved data word. The method may also include writing the at least one interleaved data word to memory in critical word order zero. The method may also include performing a check and correct operation on the at least one interleaved data word before returning the data word to a requesting device.