Interleaved FEC Across Transport Channels for Low-Latency Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional communication systems face challenges in reducing communication errors and latency over high-speed multi-wire interfaces, particularly in chip-to-chip communication, where serialization and deserialization processes introduce latency, and existing Forward Error Correction (FEC) methods may not effectively manage burst errors and latency in multi-sub-channel vector signaling codes.
Innovation Solution
The solution involves permuting the transmission order of FEC-encoded packets across multiple sub-channels in a multi-wire bus, using a permuter function to distribute FEC-encoded bits across sub-channels in a cyclically varying order, which reduces latency and enhances error correction robustness against burst errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional serialization and deserialization processes are used in high-speed multi-wire interfaces, then communication bandwidth is increased, but data latency is introduced
Solution Approach 1:
The patent segments the communication channel into multiple independent sub-channels, each capable of parallel transmission. By dividing the data stream across multiple sub-channels and processing them independently, the system achieves higher aggregate bandwidth while reducing overall latency through parallelism rather than sequential serialization.
Solution Approach 2:
The patent transitions from single-channel sequential transmission to multi-sub-channel parallel transmission, effectively adding a spatial dimension to the communication system. This dimensional expansion allows simultaneous data flow across multiple paths, increasing bandwidth without proportionally increasing latency.
2Reliability
If existing Forward Error Correction methods are applied to multi-sub-channel vector signaling codes, then error detection capability is provided, but latency is not effectively reduced and burst error robustness is insufficient
Solution Approach 1:
The patent applies Forward Error Correction encoding in advance to each sub-channel independently before transmission. This preliminary error correction preparation allows the receiver to immediately decode and correct errors without waiting for retransmission or complex post-processing, thereby reducing latency while maintaining high error detection capability.
Solution Approach 2:
The patent applies different error correction strategies to different sub-channels based on their specific characteristics. Each sub-channel receives tailored error correction treatment optimized for its local conditions, improving overall burst error robustness while minimizing the latency impact of error correction processing.
3Device complexity
If FEC-encoded packets are transmitted sequentially across sub-channels, then error correction is simplified, but latency increases and burst error robustness decreases
Solution Approach 1:
The patent merges the error correction functionality across multiple sub-channels by applying interleaving that distributes packets from the same FEC codeword across different sub-channels. This combining approach maintains relatively simple error correction logic while achieving lower latency and improved burst error robustness through the distributed transmission pattern.
Data Source
AI summary
Interleaved Forward Error Correction (FEC) encoded data from multiple FEC encoders for transport over a multi-channel physical transport medium, with cyclical rotation of the FEC encoded data bytes across transport channels in a given transmission interval as well as across time within each transport channel. A plurality of parallel FEC encoders are used to generate respective parallel FEC-encoded data streams, the outputs of which are then interleaved across a plurality of transport channels in a given transmission time interval, and, within each transport channel, the interleaved order varies over the time intervals.