Interleaved Transient Filter With Programmable Delay Tuning
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Solution Overview
Problem
Commercial integrated circuit (IC) devices are vulnerable to radiation-induced transient pulses and crosstalk, leading to performance degradation or failure, as existing fixed delay filters are large, difficult to implement, and unable to adjust delay values for process, voltage, and temperature variations.
Innovation Solution
An interleaved filter circuit with a delay element and an output buffer, utilizing complementary MOSFET transistors to mitigate Single Event Transients (SETs) by interleaving PMOSFET and NMOSFET transistors, allowing for adjustable delay configurations through programmable delay elements to accommodate varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RC filters are used to remove voltage transients, then filtering effectiveness is improved, but the filter size becomes very large and difficult to implement in modern CMOS technologies
Solution Approach 1:
The patent changes the fundamental parameters of the filter by replacing RC components with delay elements and logic gates, transforming it from an analog filter to a digital-based filter. This allows the filter to achieve transient removal functionality while occupying minimal silicon area compatible with modern CMOS processes
Solution Approach 2:
The patent substitutes the mechanical/electrical RC filter system with a digital logic-based system using delay elements and XNOR gates. This substitution enables the filter to be implemented in standard CMOS technology without requiring large external components
2Reliability
If standard C-gate filters are used to remove voltage transients, then filtering effectiveness is improved, but transients are generated at the output of the C-gate filter
Solution Approach 1:
The patent extracts the harmful transient-generating C-gate element from the filter design and replaces it with a transient-free logic gate (XNOR gate). This eliminates the source of output transients while preserving the transient removal functionality through the delay element and logic comparison approach
3Object-generated harmful factors
If SET hardened C-gates are used to mitigate transient generation, then transient generation is reduced, but the ASIC area increases significantly
Solution Approach 1:
The patent uses standard, readily available logic gates (XNOR gates) instead of expensive, area-intensive SET-hardened C-gates. The standard logic gates provide sufficient functionality for transient removal without requiring the large area overhead of hardened gates, achieving cost and area efficiency
4Reliability
If fixed delay filters are used, then transient removal is achieved, but the delay cannot be adjusted for process, voltage, and temperature variations
Solution Approach 1:
The patent introduces dynamic adjustability to the delay element, allowing the delay time to be modified based on process, voltage, and temperature conditions. This dynamic characteristic enables the filter to maintain optimal performance across varying operating conditions, transforming a static filter into an adaptive system
Data Source
AI summary
An interleaved filter circuit has a delay element configured to receive an input signal. An interleaved output buffer has a first input which receives the input signal and a second input which receives the output of the delay element. An output of the interleaved output buffer is driven when the first input and the second input are at a same logic level.