3D Interleaved Coupled Inductor Transformer for Low Parasitic Capacitance
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Solution Overview
Problem
Coupled inductors transformers face challenges in high-frequency applications due to increased parasitic capacitance, which leads to power loss and reduced efficiency.
Innovation Solution
The development of an interleaved coupled inductors transformer design, where the branches of each terminal are interleaved and made using different conductive layers of a three-dimensional integrated circuit, reducing parasitic capacitance and enhancing power transfer efficiency at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If coupled inductors transformer is used in high-frequency applications, then power transfer capability is improved, but parasitic capacitance increases causing power loss and reduced efficiency
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where multiple inductor branches are arranged in different vertical layers. This dimensional change allows inductors to be positioned above and below each other without planar overlap, reducing parasitic capacitance while maintaining power transfer capability at high frequencies
Solution Approach 2:
The transformer is divided into multiple discrete inductor branches (first branch, second branch, third branch, fourth branch) that are spatially separated and stacked in different layers. Each branch can be independently optimized and the segmentation allows for reduced coupling and lower parasitic effects compared to a monolithic structure
2Ease of manufacture
If conventional coupled inductors transformer design is used, then manufacturing is simpler, but device size is larger
Solution Approach 1:
By stacking inductor branches in the vertical dimension rather than arranging them in a planar layout, the patent achieves compact footprint integration. The multi-layer stacked configuration reduces the horizontal area occupied while maintaining the necessary inductance and coupling characteristics, enabling smaller overall device size
Solution Approach 2:
The patent implements a nested stacked structure where inductor branches are positioned in different vertical layers, with each layer containing concentric or interleaved branch configurations. This nesting approach maximizes space utilization and reduces the overall device volume while maintaining electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved power transfer efficiency and reduced parasitic capacitance, enabling operation at frequencies greater than 1 GHz with smaller dimensions, facilitating integration in ICs.
Implementation Method 1
Coupled inductors transformers are used in electronic circuits such as silicon based Integrated Circuits (ICs) for power transfer, power splitting and/or combining, impedance matching, etc.
Data Source
AI summary
An interleaved coupled inductors transformer is described in accordance with various embodiments of the present disclosure. In various embodiments, the interleaved coupled inductors transformer includes a first terminal including a first port, a first branch of the first terminal, and a second branch of the first terminal approximately parallel to with the first branch of the first terminal. The interleaved coupled inductors transformer includes a second terminal spatially separate from the first terminal, the second terminal including a second port, a first branch of the second terminal, a second branch of the second terminal approximately parallel to with the first branch of the second terminal, wherein the first and second branches of the first terminal do not overlap with the first and second branches of the second terminal.