Interleaved Latch Regulator for Low-Ripple Charge Pumps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Charge pump regulators face challenges in minimizing output voltage ripple due to discrete sampling in latched comparators, leading to increased overshoot or undershoot, which is exacerbated by the need for high output capacitance and longer response times.
Innovation Solution
The implementation of a skip-mode regulator with a comparator featuring four interleaved latches that perform multiple comparisons per clock cycle, reducing response time and output voltage ripple without increasing capacitance, by using a clock generator to output equally-delayed secondary clock signals and control logic to manage timing signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a latched comparator with discrete sampling is used, then the regulator can maintain voltage control, but the output voltage ripple increases due to delayed response
Solution Approach 1:
The single latched comparator is segmented into multiple interleaved latched comparators (first, second, third, and fourth latched comparators) that operate at different phases. This segmentation allows the system to perform multiple voltage comparisons within one clock cycle, reducing the effective response time and thereby decreasing output voltage ripple while maintaining accurate voltage control.
2Loss of time
If the response time of the regulator is decreased, then the output voltage ripple is reduced, but the discrete sampling nature causes missed latch signals and increased overshoot/undershoot
Solution Approach 1:
Multiple latched comparators are configured to operate periodically at different phases within each clock cycle. The first latched comparator operates at phase 0, the second at phase 90 degrees, the third at phase 180 degrees, and the fourth at phase 270 degrees. This periodic interleaved operation ensures that voltage comparisons are performed at multiple time points throughout each cycle, capturing transient conditions that a single comparator might miss while maintaining reliable signal latching.
3Productivity
If multiple interleaved latched comparators are used, then the response time is reduced and output ripple decreases, but the device complexity increases
Solution Approach 1:
Multiple latched comparators are merged into a single integrated voltage regulation system with shared control logic and clock distribution. The interleaved latched comparators work in unison under coordinated control signals, allowing the system to achieve fast response times and reduced output ripple while managing complexity through unified architecture rather than independent comparator circuits.
Data Source
AI summary
A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).