Interleaved Super-Junction Load Switches for Lower On-Resistance
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Solution Overview
Problem
Existing high voltage load switches with back-to-back connected LDMOS devices quadruple the specific on-resistance (Rsp) due to doubled device area and on-resistance, making them inefficient for integrated circuits.
Innovation Solution
A load switch design featuring a pair of back-to-back connected transistors with comb-shaped gates and shared drain/source regions, where the fingers of the gates are arranged in an alternating manner to reduce the footprint and improve efficiency, utilizing a shared high voltage oxide region and comb structures to form a super-junction like transistor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If back-to-back connected LDMOS devices are used for high voltage load switch, then bidirectional current blocking capability is achieved, but the specific on-resistance quadruples due to doubled device area
Solution Approach 1:
The patent merges two LDMOS devices into a single integrated structure with shared drain and source regions. The comb-shaped gates of both devices are formed in an alternating interleaved manner within a single device area, allowing bidirectional current blocking while reducing the total device area and specific on-resistance compared to separate back-to-back connected devices
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional comb-shaped gate structure with interleaved fingers. This vertical stacking and interleaving of gate fingers in the third dimension allows both transistors to share the same footprint area, effectively reducing the device area and specific on-resistance while maintaining bidirectional blocking capability
2Reliability
If back-to-back connected LDMOS devices are used for high voltage load switch, then bidirectional current blocking is achieved, but the device footprint increases
Solution Approach 1:
The patent combines two separate LDMOS devices into one integrated device with shared drain and source regions. The comb-shaped gates are formed in an alternating interleaved manner within a single device footprint, effectively halving the required area compared to separate back-to-back connected devices
Solution Approach 2:
The comb-shaped gate structure with interleaved fingers utilizes vertical stacking and three-dimensional spatial arrangement to pack both transistor gates into a smaller footprint. This dimensional approach allows overlapping gate structures that would not be possible in a simple planar layout, reducing the overall device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the effective specific on-resistance by over 50% compared to conventional devices, improving the efficiency and cost-effectiveness of high voltage load switches for integrated circuits.
Implementation Method 1
The plurality of vertical PN junctions helps to confine the electric field in the lightly doped n-type epitaxial layer
Implementation Method 2
The plurality of vertical PN junctions also helps to reduce the switching power losses through achieving unique non-linear parasitic capacitance characteristics
Data Source
AI summary
An apparatus includes a first drain/source region and a second drain/source region over a substrate, a first gate adjacent to the first drain/source region, the first gate comprising a plurality of first fingers forming a first comb structure, and a second gate adjacent to the second drain/source region, the second gate comprising a plurality of second fingers forming a second comb structure, wherein the plurality of first fingers and the plurality of second fingers are placed in an alternating manner, and wherein the first drain/source region, the second drain/source region, the first gate and the second gate form two back-to-back connected transistors.