Interleaved Quad-Channel Memory Module for Higher DDR Bandwidth
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Solution Overview
Problem
Existing memory systems face challenges in achieving high bandwidth performance due to limitations in data communication rates between memory devices and channels, particularly in dual-channel configurations.
Innovation Solution
A quad-channel memory module with interleaved data communication, utilizing data buffer devices to multiplex and demultiplex data between channels and ranks, enabling operation at a quad-data rate (QDR) while maintaining independent access to non-overlapping sets of memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-channel memory devices are used with independent access to non-overlapping memory arrays, then reliability and independent access are improved, but bandwidth is limited by the data communication rate between memory devices and channels
Solution Approach 1:
Data buffer devices are introduced as intermediaries between the memory devices and the channels. These buffers receive data from memory devices at one data rate and output data to channels at a higher data rate, effectively decoupling the memory device interface from the channel interface and enabling bandwidth enhancement without changing the memory device architecture.
Solution Approach 2:
The patent changes the data communication parameter by implementing time-interleaved data communication where data is transmitted at quad-data rate (QDR) through the channels while memory devices operate at double-data rate (DDR). This parameter change in data rate is achieved through the coordinated operation of multiple memory ranks and channels with proper timing.
2Productivity
If data buffer devices multiplex and demultiplex data between channels and ranks, then bandwidth is enhanced to QDR, but device complexity increases
Solution Approach 1:
The memory system is segmented into multiple independent ranks (first rank and second rank) with separate memory arrays. Each rank can be independently accessed through dedicated channels, allowing parallel data communication paths. This segmentation enables the system to achieve higher aggregate bandwidth while keeping individual components manageable.
Solution Approach 2:
The data buffer devices implement periodic time-interleaved data communication where data from multiple ranks is multiplexed in a periodic manner onto channel data paths. This periodic action allows efficient use of channel bandwidth by alternating between different data sources in a systematic pattern, achieving QDR without requiring simultaneous data paths for all ranks.
Data Source
AI summary
A four-channel by two ranks-per-channel memory module includes four independent memory channels and dual-channel memory devices. The channels of the dual-channel memory module devices may be accessed independently. Thus, the four channels for accessing the memory module may each concurrently access, via a one of the two channels of the memory devices, a respective first rank and a second rank. Data buffer devices on the memory module communicate data between the two ranks and the channels. The data buffer devices multiplex/demultiplex (a.k.a., interleave/deinterleave) communication between the channels and the ranks so that the channels operate at a greater bandwidth (e.g., quad-data rate—QDR) than the memory devices (e.g., double-data rate—DDR). The data buffer devices also retime and/or redistribute data strobe signals communicated between the memory devices and the channels.