Interleaved Memory Cell Block Testing Method
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Solution Overview
Problem
Conventional memory device testing methods require a long time to detect process defects, particularly in memory cell blocks, due to the sequential testing of each block, which is inefficient and time-consuming.
Innovation Solution
A method that activates and tests memory cell blocks in an interleave pattern, alternating between odd-numbered and even-numbered blocks, allowing simultaneous sense, read, and precharge operations across multiple word lines, reducing the overall test time by performing these operations in a predetermined time period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cell blocks are tested sequentially one after another, then each block can be thoroughly tested, but the total test time becomes very long
Solution Approach 1:
The memory device is divided into multiple memory cell blocks (first block, second block, third block, etc.), and the testing process is segmented into parallel operations on different blocks. This allows simultaneous testing of multiple blocks rather than sequential testing, significantly reducing total test time while maintaining thoroughness.
Solution Approach 2:
The testing approach transitions from a single-dimensional sequential process to a multi-dimensional parallel process. By introducing temporal parallelism and operating on multiple blocks simultaneously across different time periods, the system achieves both thorough testing and reduced total time.
2Device complexity
If sequential testing is performed for each memory cell block, then testing complexity is low, but productivity is reduced due to long test time
Solution Approach 1:
The testing system is segmented into multiple independent testing units that can operate simultaneously on different memory cell blocks. Each block has its own testing sequence (active, write, precharge operations), allowing parallel execution and improving productivity without significantly increasing overall system complexity.
Solution Approach 2:
The testing method employs periodic actions where different memory blocks are tested in alternating time periods. The first block is tested during a first time period, then the second block during a second time period, and so on. This periodic parallel testing maintains manageable complexity while dramatically improving testing speed.
3Loss of time
If multiple memory cell blocks are tested simultaneously, then test time is reduced, but the control and coordination complexity increases
Solution Approach 1:
The control system is segmented into separate control units for each memory cell block, with each unit independently managing its own testing sequence. This segmentation allows simultaneous testing of multiple blocks while keeping individual control complexity manageable through modular architecture.
Solution Approach 2:
The testing system dynamically switches between different memory blocks based on time periods. The control mechanism dynamically activates different blocks in a predetermined sequence, allowing flexible coordination of parallel testing operations. This dynamic approach manages complexity through time-based scheduling rather than simultaneous control of all blocks.
Data Source
AI summary
Disclosed is a method for testing a memory device, which can test a memory cell block while testing another memory cell block, so as to catch a process defect of the memory device within a short time period, thereby reducing the test time. The method for testing a memory device provided with a bank including N memory cell blocks and sense amplifiers, the method comprising the steps of: a) expressing the N memory cell blocks as a first, a second, . . . , an Nth memory cell block; b) sequentially activating odd-numbered memory cell blocks of the N memory cell blocks one by one in a predetermined time period; c) performing sense, read (or write) and precharge operations for each activated memory cell block; and d) performing steps a) to c) for even-numbered memory cell blocks after tests for all the odd-numbered memory cell blocks are finished.