Interleaved Memory Channel Layout for Low-Crosstalk Routing
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Solution Overview
Problem
As the number of memory channels increases in modern computing devices, routing traces between the host and memory devices become complex, leading to issues such as insertion loss, return loss, and cross talk, which degrade device performance, and conventional solutions involving additional trace layers increase manufacturing costs and size.
Innovation Solution
Interleaving different sets of memory channels within a host circuitry to reduce the complexity of traces, requiring only two layers in the fan-out package while maintaining direct pin-to-pin connections, thereby minimizing trace length and cross talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory channels is increased, then memory bandwidth and performance are improved, but trace complexity and routing difficulty increase
Solution Approach 1:
The patent segments memory channels into distinct groups (first set of memory channels including first and second memory channels, second set of memory channels including third and fourth memory channels) that can be independently routed. This segmentation allows each group to be managed separately, reducing overall routing complexity while maintaining high memory bandwidth through parallel channel operation.
Solution Approach 2:
The patent utilizes multiple physical layers in the PCB to route memory traces. By transitioning from a single-layer to a multi-layer trace architecture, the patent resolves routing complexity by distributing traces across different dimensional planes, allowing increased memory channels to be routed without excessive crowding in any single layer.
2Reliability
If additional trace layers are added to handle complex routing, then signal integrity is improved, but manufacturing cost and device size increase
Solution Approach 1:
The patent merges multiple memory channel traces into shared PCB layers where feasible, rather than dedicating separate layers to each channel. The first and second sets of memory channels share common trace layers, reducing the total number of layers required while maintaining signal integrity through proper layer stacking and impedance control.
Solution Approach 2:
The patent applies different trace routing strategies to different regions of the PCB based on local requirements. Critical high-frequency traces receive enhanced shielding and spacing in specific areas, while less critical connections use standard routing. This localized optimization maintains signal integrity where needed without unnecessarily increasing manufacturing complexity across the entire board.
3Adaptability or versatility
If memory channels are routed through long traces, then connection flexibility is improved, but insertion loss and cross talk increase
Solution Approach 1:
By utilizing multiple PCB layers, the patent shortens the physical trace length required to connect memory channels to the memory circuitry. Traces that would otherwise need to span large distances on a single layer can instead use vertical transitions between layers, reducing trace length and consequently reducing insertion loss and cross-talk while maintaining connection flexibility.
Solution Approach 2:
The patent uses PCB vias and intermediate connection points as mediators between memory channels and the memory circuitry. These intermediary elements allow traces to change direction and layer efficiently, reducing the need for long, meandering traces while maintaining adaptability in the routing layout.
Data Source
AI summary
A memory system includes a host circuitry coupled to a memory circuitry, the host circuitry including a first set of memory channels comprising first memory channels and second memory channels that are interleaved with one another, and a second set of memory channels comprising third memory channels and fourth memory channels that are interleaved with one another.