Interleaved Memory Codewords for Localized Error Detection
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Solution Overview
Problem
Existing memory device transmission methods are limited in detecting multi-bit errors due to localized interference, which can cause errors in only one codeword while leaving others unaffected, leading to incomplete error detection in data transmissions between memory devices and host devices.
Innovation Solution
Implementing interleaved codeword transmission by generating and transmitting error protection codes for data sets in an alternating or checkerboard pattern across different unit intervals and data channels, increasing the likelihood that localized interference affects multiple codewords and enhances the probability of detecting multi-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If codewords are transmitted consecutively in traditional memory devices, then transmission speed is maintained, but localized interference can cause multi-bit errors in only one codeword, reducing error detection reliability
Solution Approach 1:
The transmission system segments codewords into separate transmission groups with different interleaving patterns. First codewords use one pattern while second codewords use another pattern, allowing error detection to benefit from diversified transmission paths without requiring complete restructuring of the memory device architecture
Solution Approach 2:
The system implements periodic alternation between different codeword transmission patterns. By alternating first and second codewords in different patterns across transmission intervals, the system ensures that localized interference affecting one pattern is less likely to affect all codewords uniformly, thereby improving multi-bit error detection while maintaining regular transmission timing
2Reliability
If interleaved codeword transmission is implemented, then probability of detecting multi-bit errors increases, but transmission protocol complexity increases
Solution Approach 1:
The error detection mechanism is segmented into separate handling paths for first and second codewords. The host device processes first codewords with one validation approach and second codewords with another, simplifying the implementation of complex interleaved patterns by breaking down the overall protocol into manageable, distinct operational segments
Solution Approach 2:
The system performs preliminary classification of codewords into first and second categories before transmission. By pre-establishing which codeword pattern to use based on codeword type or position, the system simplifies real-time transmission decisions and error detection logic, making the interleaved protocol easier to implement without sacrificing error detection effectiveness
Data Source
AI summary
Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.