Memory Array Error Correction in Interleaved Column Cycles
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Solution Overview
Problem
Existing memory devices face performance penalties due to the need for frequent refresh operations to prevent data corruption from leakage in DRAM, which consumes power and interrupts read/write operations, and existing error correction schemes compromise operational speed and circuit real estate.
Innovation Solution
The solution involves dividing the column cycle into two halves to allow for error correction and check bit regeneration during an interleaved column cycle, enabling extended refresh time intervals and reducing the frequency of refresh operations, while maintaining fast clock rates for data operations by interleaving read, modify, and write processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent data corruption from leakage in DRAM, then data reliability is improved, but power consumption increases and read/write operations are interrupted
Solution Approach 1:
The column cycle is divided into two halves: a first half for read operations and a second half for write operations. This segmentation allows error correction and check bit regeneration to be performed during the transition between halves, enabling extended refresh intervals without compromising data reliability or increasing power consumption
2Reliability
If error correction schemes are implemented to enhance memory array data storage reliability, then data reliability is improved, but operational speed and circuit real estate are penalized
Solution Approach 1:
Check bits are regenerated and error correction is performed in advance during the transition between read and write halves of the column cycle. This preliminary action ensures data reliability is maintained while operational speed is preserved, as error correction does not interrupt the main data operations
Solution Approach 2:
The error correction process is integrated into the continuous column cycle operation, where check bit regeneration occurs during the natural transition between read and write phases. This maintains continuous useful action without interrupting data streams or reducing operational speed
3Reliability
If error correction and check bit regeneration are performed during column cycles, then data reliability is improved, but the column cycle time is extended
Solution Approach 1:
The column cycle is segmented into distinct read and write halves with error correction performed during the transition. This segmentation allows error correction to be embedded within the existing cycle structure rather than adding to it, maintaining fast clock rates while ensuring data reliability
Data Source
AI summary
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.