Interleaved Memory ECC for Fast Error Detection and Correction
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Solution Overview
Problem
Existing error correction and detection methods in memory devices require increased hardware resources and processing time, which can lead to delays and system failures in real-time systems, especially when dealing with memory faults.
Innovation Solution
The system employs an interleaved code word with an equal number of check bits and data bits, using a check bit generator, syndrome bit generator, and correction bit generator to detect and correct errors, with an uncorrectable error detector to identify uncorrectable errors, allowing for efficient error correction and detection in memory words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes are used to detect and correct memory errors, then reliability is improved, but processing time increases
Solution Approach 1:
The code word is segmented into data bits and check bits that are interleaved rather than stored separately. This segmentation allows the syndrome calculation to proceed in parallel by distributing check bits across the data bit positions, enabling simultaneous error detection across multiple bit positions without sequential processing delays.
Solution Approach 2:
Check bits are generated and interleaved with data bits during the write operation to memory. This preliminary action ensures that error detection capability is already in place when the read operation occurs, eliminating the need for separate check bit generation during reading and reducing processing time during critical read operations.
2Reliability
If error correcting codes are used to detect and correct memory errors, then reliability is improved, but hardware resources increase
Solution Approach 1:
The same interleaved code word structure serves multiple functions: it enables error detection, supports error correction, and maintains compact storage. The check bits interleaved with data bits universally serve both as error detection indicators and as part of the corrected data reconstruction process, eliminating the need for separate hardware circuits for different error handling functions.
Solution Approach 2:
The error detection and correction capability is achieved by adding a temporal/dimensional aspect to the storage structure through interleaving. Instead of adding redundant hardware circuits in the spatial dimension, the patent distributes check bits across time positions in the interleaved sequence, effectively using the time dimension to provide error protection without increasing spatial hardware complexity.
3Reliability
If traditional error correcting codes are used, then error detection capability is improved, but execution rate slows down
Solution Approach 1:
The syndrome calculation is segmented into independent operations that can be performed in parallel by distributing check bits across different positions. Each check bit contributes to specific syndrome calculations independently, allowing the processor to calculate multiple syndrome bits simultaneously rather than sequentially, thereby maintaining high execution rates while preserving error detection capability.
Solution Approach 2:
The interleaved structure is prepared in advance during the write operation, so that during the read operation, the error detection and correction can proceed directly without needing to generate or reorganize check bits. This preliminary organization of data and check bits enables immediate syndrome calculation and error correction, maintaining processor execution rate.
Data Source
AI summary
Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.