Interleaved Memory Plane Operations for Power Stability
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Solution Overview
Problem
Current memory systems face challenges in reducing manufacturing costs while maintaining performance and reliability, particularly in managing interleaving operations across multiple memory planes, which can lead to data input/output performance degradation and power management issues during erase operations.
Innovation Solution
A memory system with a controller that enables interleaving operation modes across multiple memory planes, allowing simultaneous or sequential execution of read, program, and check operations while performing an erase operation on one plane, thereby optimizing command sequences and preventing simultaneous erase operations across planes to manage power and improve data I/O performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interleaving operations are performed across multiple memory planes, then data I/O performance is improved, but power management issues and reliability risks occur during erase operations
Solution Approach 1:
The memory device is divided into multiple independent planes, each capable of performing operations independently. The controller segments erase operations to occur only in one plane at a time, while other planes perform read/program/check operations, thus isolating power-intensive operations to prevent system-wide power instability.
Solution Approach 2:
The interleaving operation alternates between different planes in a periodic manner. While one plane undergoes erase operation, other planes perform different operations, and this pattern cycles through all planes. This periodic alternation distributes power consumption over time and prevents simultaneous power demands across all planes.
2Ease of manufacture
If simultaneous erase operations are performed across multiple planes, then manufacturing cost is reduced, but power instability and data loss risk increase
Solution Approach 1:
Erase operations are segmented to occur in only one plane at a time rather than simultaneously across all planes. This segmentation of the erase operation timeline prevents excessive simultaneous power consumption while still utilizing multiple planes for parallel read/program/check operations, achieving cost efficiency without compromising power stability.
Solution Approach 2:
The controller preliminarily determines and schedules erase operations to be performed sequentially across different planes before executing them. This preliminary scheduling ensures that erase operations are properly spaced in time to avoid power instability, while other operations can be prepared in advance in different planes.
3Device complexity
If multiple operations are performed simultaneously on the same memory plane, then device complexity is reduced, but operation conflicts and performance degradation occur
Solution Approach 1:
The system transitions from temporal dimension (sequential operations on one plane) to spatial dimension (parallel operations across multiple planes). By distributing operations across multiple planes simultaneously, the system achieves higher throughput without increasing control logic complexity, as each plane operates independently under unified controller management.
Data Source
AI summary
A memory system includes a first memory die including multiple planes each including a plurality of memory cells and a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die. After transferring an erase command to a plane among the multiple planes, the controller transfers a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane.