Interleaved Memory Routing Without Address Modification
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Solution Overview
Problem
Network on Chip (NoC) systems face challenges in efficiently managing interleaved memory regions, particularly in balancing traffic and maintaining address integrity across multiple channels, which can disrupt security features and increase system costs.
Innovation Solution
A method and apparatus that determine the appropriate destination for memory transactions within interleaved regions by calculating the destination based on the address, step size, number of destinations, and offset, using formulas such as (address[log 2(MCChS)−1, log 2(the step size)]+the offset) modulo the number of destinations, allowing for efficient routing without modifying the original address, thereby supporting flexible and balanced memory access across multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If address modification is used to route transactions to appropriate destinations in interleaved memory regions, then traffic balancing across channels is improved, but address integrity is compromised and security features are disrupted
Solution Approach 1:
The patent segments the address routing function by separating the destination determination logic from the address itself. It uses segmentation of the interleaved memory region into multiple channels, where each channel is identified by calculating which channel should service a given address without modifying the address. The routing is segmented by using channel identification based on address ranges and modulo operations to determine the appropriate destination channel.
2Productivity
If complex routing logic is implemented to manage interleaved memory regions, then traffic balancing is improved, but device complexity increases
Solution Approach 1:
The patent changes parameters to simplify routing by using configurable parameters such as channel identification values, address range definitions, and step sizes. Instead of complex algorithms, it uses parameter-based routing where the destination channel is determined by comparing the address against configured ranges and applying simple modulo arithmetic. The system allows dynamic configuration of interleaved region parameters without requiring complex hardwired logic.
3Adaptability or versatility
If interleaved memory regions are supported with multiple destinations, then memory access flexibility is improved, but system cost increases
Solution Approach 1:
The patent implements multi-functionality by designing a universal routing mechanism that handles both interleaved and non-interleaved memory regions using the same infrastructure. The apparatus can service multiple destinations (channels) through a single unified routing logic that adapts based on the memory region type. This universal approach allows the system to support flexible memory access patterns without requiring separate dedicated hardware for each memory type, thereby reducing overall system cost.
Data Source
AI summary
A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.