Interleaved MEOL Linear Capacitor Layout for Higher Density
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Solution Overview
Problem
There is a need for high density linear capacitors in semiconductor technologies to reduce integrated circuit chip area while maintaining linearity, as existing metal-oxide-metal capacitors have low density and metal oxide semiconductor capacitors are highly nonlinear.
Innovation Solution
The design incorporates interleaved MEOL interconnects on MEOL layers to form high density linear capacitors, with interleaved gate interconnects and oxide diffusion regions, and optionally shielded nodes to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal-oxide-metal capacitors are used, then manufacturing is easier, but density is low
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional vertically stacked capacitor structures. Multiple capacitor stacks are formed by stacking conductive layers and dielectric layers vertically, thereby increasing the effective capacitance area without increasing the horizontal chip area. This dimensional transition directly resolves the contradiction by achieving higher density while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor units are stacked vertically within the same footprint area. Each capacitor stack contains multiple conductive plates separated by dielectric layers, with smaller capacitor units nested within the vertical space occupied by larger ones. This nesting approach increases the quantity of capacitive elements per unit area, thereby improving density without complicating the manufacturing process.
2Quantity of substance
If metal oxide semiconductor capacitors are used, then density is higher, but linearity is poor
Solution Approach 1:
The patent employs composite capacitor structures combining metal layers and oxide layers in alternating stacks. The metal layers provide high conductivity and linearity, while the oxide layers provide high dielectric constant for increased density. By composite stacking these materials vertically, the invention achieves both high density from the oxide layers and good linearity from the metal layers, resolving the contradiction between these two properties.
Solution Approach 2:
The patent segments the capacitor structure into multiple discrete layers of alternating metal and oxide materials. Each layer is independently formed and controlled, allowing optimization of each material's properties. The metal segments provide linear voltage-capacitance characteristics while the oxide segments contribute to high density, and their segmented stacking enables both properties to coexist in the overall capacitor structure.
3Quantity of substance
If capacitor size is increased to improve density, then parasitic capacitance increases
Solution Approach 1:
The patent increases capacitance density by extending capacitor structures in the vertical dimension rather than horizontally. Multiple capacitor stacks are formed vertically, increasing the effective capacitance without increasing the horizontal footprint. This vertical extension avoids increasing parasitic capacitance associated with larger horizontal interconnect lengths, thereby resolving the contradiction between density improvement and parasitic reduction.
Solution Approach 2:
The patent incorporates shielding structures and careful layout design to preemptively reduce parasitic capacitance effects. Ground shielding layers are placed adjacent to signal interconnects to shield against parasitic coupling. The interleaved finger structure is designed with attention to minimizing overlapping parasitic areas. These beforehand cushioning measures allow the capacitor density to be increased without proportionally increasing parasitic capacitance.
Data Source
AI summary
A device includes a first plurality of MEOL interconnects coupled to a second node that extends in a first direction. The first plurality of MEOL interconnects includes first and second subsets of MEOL second-terminal interconnects. The device includes a second plurality of MEOL interconnects coupled to a first node that extends in the first direction. The second plurality of MEOL interconnects includes first and second subsets of MEOL first-terminal interconnects. The first subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a first subset of interleaved MEOL interconnects. The second subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a second subset of interleaved MEOL interconnects. The device includes at least one of a first plurality of gate interconnects or a first plurality of OD regions extending in a second direction orthogonal to the first direction between the first and second subsets of interleaved MEOL interconnects.