Interleaved On-Chip Inductor Core Array for High Flux Density
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Solution Overview
Problem
The challenge in semiconductor integrated circuits is the limited ability to fabricate high-value inductors on-chip, leading to the reliance on expensive and space-consuming off-chip discrete inductors, which are not suitable for compact applications like smartphones or PDAs.
Innovation Solution
A method for forming an array of inductor core elements on a semiconductor substrate, where two sets of metallic core elements are interleaved with isolation sidewalls, allowing for efficient magnetic coupling and energy storage, and fabricated using electroplating techniques with multiple metal layers and different materials to optimize inductance and minimize losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If off-chip discrete inductors are used, then sufficient flux and energy storage is achieved, but system cost increases and space requirements increase
Solution Approach 1:
The patent transitions from planar 2D inductor layouts to 3D vertically stacked configurations. Multiple inductor windings are arranged in different vertical layers (first winding in lower layer, second winding in upper layer) with magnetic cores positioned between them, enabling sufficient flux generation within a compact footprint by utilizing the vertical dimension.
Solution Approach 2:
The patent implements nested inductor structures where one inductor winding is positioned within the magnetic field region of another. The first winding and second winding are arranged such that their magnetic fields overlap and interact, with magnetic cores nested between the windings, effectively multiplying the flux generation capability within the same planar area.
2Loss of energy
If off-chip discrete inductors are used, then sufficient energy storage is achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple inductor functions into a single integrated on-chip structure. The first winding, second winding, and magnetic cores are all fabricated together on the same semiconductor substrate using compatible processes, eliminating the need for separate off-chip inductor components and reducing overall manufacturing cost.
Solution Approach 2:
The patent employs electroplating techniques to precisely control the thickness and dimensions of metal windings and magnetic core structures. By adjusting plating parameters such as current density, plating time, and bath composition, the inductance values and quality factors can be optimized to match design specifications while maintaining cost-effective manufacturing.
3Device complexity
If traditional planar inductor structures are used, then fabrication is simple, but inductance value is limited
Solution Approach 1:
The patent extends the inductor structure into the vertical dimension with multiple stacked windings and magnetic cores. This 3D configuration increases the effective magnetic path length and flux density without significantly increasing planar footprint, thereby achieving higher inductance values compared to traditional planar structures.
Solution Approach 2:
The patent utilizes composite magnetic core structures made from different magnetic materials with complementary properties. The magnetic cores are positioned between and around the windings to enhance magnetic flux confinement and reduce core losses, achieving superior inductance performance through material composition optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of high-value inductors on-chip, reducing costs and size constraints, while enhancing energy storage capacity and minimizing core losses, resulting in a compact and efficient power regulator system.
Implementation Method 1
A first metal material is electroplated into the recesses to form a first set of spaced apart core elements
Implementation Method 2
By applying a current through the inductor, the magnetic flux is created
Data Source
AI summary
The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.