Interleaved On-Chip Testing of Digital and Analog Subsystems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current serial testing methods for system-on-chip (SoC) devices in wireless devices are inefficient and do not simulate real-world concurrent operation of digital and analog subsystems, leading to time-consuming and unrealistic testing scenarios, especially in automotive and communication applications.
Innovation Solution
An interleaved on-chip testing method that merges test setups for analog and digital components, allowing concurrent execution via a unified mode of operation using a system-on-chip test access port (SoC TAP), memory test access port (MTAP), built-in self-test (BIST) controller, phase locked loop (PLL), and multiplexer, enabling simultaneous testing of digital and analog subsystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial testing architecture is used to test digital and analog subsystems separately, then testing can be performed with dedicated modes, but testing time is significantly increased and real-world concurrent operation is not simulated
Solution Approach 1:
The patent merges separate test setups for digital and analog subsystems into a unified test architecture. The SoC TAP controller coordinates both digital memory tests and analog PLL tests through a single integrated interface, eliminating the need for separate dedicated test modes and reducing overall testing time while maintaining comprehensive coverage of both subsystems
Solution Approach 2:
The patent implements continuous interleaved testing where digital and analog tests are executed concurrently rather than sequentially. The controller alternates between digital memory operations and analog PLL operations in an interleaved manner, ensuring that both subsystems are tested continuously without idle waiting periods, thereby reducing total test time while maintaining test reliability
2Ease of manufacture
If serial testing modes are used with dedicated test setups, then each subsystem can be tested independently, but the testing process does not replicate field use or system level use cases
Solution Approach 1:
The patent creates a universal test interface (SoC TAP) that can handle both digital and analog testing functions through a single integrated controller. This multi-functional approach allows the same test setup to replicate various field use scenarios including concurrent digital-memory and analog-PLL operations, making the test system both simple to manufacture and highly adaptable to different real-world operating conditions
3Device complexity
If separate test modes are used for digital and analog subsystems, then testing can be performed with dedicated interfaces, but the same testing pins must be reused which is time consuming
Solution Approach 1:
The patent combines multiple test interfaces (SoC TAP and MTAP) into a unified test architecture where a single controller can manage both digital and analog testing through shared pins. This merging eliminates the need to physically reconfigure or switch between separate dedicated test setups, thereby maintaining manageable device complexity while dramatically improving testing efficiency through concurrent operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces testing time, provides a more realistic simulation of real-world operations, and identifies interactions between subsystems, enhancing efficiency and accuracy in testing wireless devices and automotive systems.
Implementation Method 1
A multiplexer is also included and is in communication with the memory and a phase locked loop (PLL) through an AND gate
Data Source
AI summary
The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.