Interleaved Parity Error Detection for CRAM Memory Arrays
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Solution Overview
Problem
Conventional error detection circuitry in programmable integrated circuits is slow due to sequential data processing, leading to inefficient error detection and correction in large arrays of configuration random-access-memory (CRAM) cells, which can result in frequent disruptions and power consumption issues when soft errors occur.
Innovation Solution
The implementation of error detection circuitry using logic XOR gates arranged in linear chains or binary trees, with interleaved structures for single-bit or multi-bit error detection, and error correction circuitry that corrects errors more efficiently by scanning columns rapidly and correcting them in a pipelined manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential error detection circuitry is used, then the circuit complexity is relatively simple, but the error detection speed is slow leading to frequent disruptions
Solution Approach 1:
The patent divides the error detection circuit into multiple parallel processing paths, each handling a portion of the CRAM cell data simultaneously. This segmentation allows the system to process large arrays of configuration data in parallel rather than sequentially, dramatically improving error detection speed while distributing circuit complexity across multiple manageable units
Solution Approach 2:
The patent transitions from one-dimensional sequential processing to multi-dimensional parallel processing by organizing error detection circuitry across multiple dimensions - spatial parallelism through distributed detection units, temporal parallelism through pipelined architectures, and hierarchical parallelism through tree-structured aggregation. This dimensional expansion enables exponential improvement in processing capacity
2Use of energy by moving object
If conventional sequential error detection is used, then the device can operate normally, but power consumption increases due to frequent reloading
Solution Approach 1:
The patent implements continuous error detection and correction operations that run concurrently with normal device operation. The parallel error detection circuitry continuously monitors CRAM cell states without interrupting the functional operation of the programmable device, eliminating the need for frequent stop-and-reload cycles that consume excessive power
3Productivity
If faster error detection circuitry is implemented, then error detection speed improves, but the circuit complexity and area increase
Solution Approach 1:
The patent combines multiple functions into unified error detection units that can process different types of errors (single-bit, multi-bit, adjacent cell errors) through the same parallel processing infrastructure. By merging detection, localization, and correction functions into integrated units, the system achieves high throughput without proportionally increasing circuit area
Solution Approach 2:
The patent designs universal error detection blocks that can handle various error scenarios through configurable logic. These multi-functional units can detect single-bit errors, multi-bit errors, and adjacent cell errors by adjusting their operation mode, eliminating the need for separate dedicated circuits for each error type and reducing overall area requirements
Data Source
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AI summary
Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.