Interleaved Parity Error Detection Circuits for Soft Error Correction

Solution Overview

Problem

Conventional error detection circuitry in programmable integrated circuits is slow in detecting soft errors due to sequential data checking, requiring a large number of clock cycles to process data bits, which can lead to frequent disruptions and power consumption issues when reloading configuration data.

Innovation Solution

The integration of error detection circuitry with logic XOR gates arranged in linear chains or binary trees, allowing for rapid detection of single-bit or multi-bit errors through interleaved structures and pipelining, enabling faster error detection and correction by processing multiple data bits in parallel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional sequential error detection circuitry is used, then the circuit complexity is low, but the error detection speed is slow requiring more than 100 million clock cycles

Engineering Contradiction:

Improveerror detection speedVSAvoidcircuit complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent divides the error detection process into multiple parallel segments using separate error detection circuits for different data bit groups (e.g., first group of data bits, second group of data bits). Each segment processes a portion of the configuration data simultaneously, reducing the total detection time from sequential processing to parallel processing while maintaining manageable circuit complexity for each segment.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from one-dimensional sequential error detection to multi-dimensional parallel detection by organizing multiple error detection circuits to operate simultaneously on different data groups. This dimensional expansion allows the system to process N bits of configuration data in parallel rather than sequentially, achieving the speed improvement without proportionally increasing overall system complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the entire programmable device is reloaded when an error is detected, then error correction is achieved, but frequent disruptions and power consumption occur

Engineering Contradiction:

Improveerror correction capabilityVSAvoidoperational disruptions

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and corrects only the specific erroneous data bits identified by the error detection circuits, rather than reloading the entire configuration data. When an error is detected in a particular group of data bits, only that specific group is reloaded from the configuration data, minimizing operational disruptions and power consumption while maintaining reliability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by performing error correction only on the affected portions of configuration data rather than the entire dataset. The error detection and correction mechanism selectively targets only the data bits that contain errors, avoiding unnecessary reloading of error-free data and reducing the frequency and duration of disruptions.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If the entire programmable device is reloaded when an error is detected, then error correction is achieved, but significant power consumption occurs

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts and corrects only the specific erroneous data bits identified by the error detection circuits, rather than reloading the entire configuration data. When an error is detected in a particular group of data bits, only that specific group is reloaded from the configuration data, minimizing operational disruptions and power consumption while maintaining reliability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by performing error correction only on the affected portions of configuration data rather than the entire dataset. The error detection and correction mechanism selectively targets only the data bits that contain errors, avoiding unnecessary reloading of error-free data and reducing the frequency and duration of disruptions.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8984367B2Error detection and correction circuitry

Publication Date: 2015.03.17 ALTERA CORP

AI summary

Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.