Interleaved Parity Circuit for Low-Latency Error Detection
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Solution Overview
Problem
As integrated circuit operating frequencies increase, the incidence of incorrectly transmitted bits also rises, leading to increased parity latency and the need for faster error detection and asynchronous parity correctness signaling to maintain high operating frequencies.
Innovation Solution
An interleaved parity computation circuit that includes multiple parity circuits and a combining circuit, which interleaves parity computations across alternating clock cycles to reduce latency and provide asynchronous signals for error detection, allowing for quicker error handling and increased operating frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating frequency is increased, then productivity is improved, but reliability deteriorates due to increased incorrectly transmitted bits
Solution Approach 1:
The patent divides the single parity checking operation into multiple segments by using multiple parity circuits (first parity circuit and second parity circuit) that operate on alternating clock cycles. This segmentation allows the system to maintain high operating frequencies while ensuring transmission accuracy through distributed parallel checking.
2Productivity
If operating frequency is increased, then productivity is improved, but parity latency increases
Solution Approach 1:
The patent implements periodic action by having the first and second parity circuits operate on alternating clock cycles (odd and even cycles respectively). This periodic distribution of parity checking tasks reduces the latency for each individual checking operation while maintaining high overall operating frequency through continuous parallel processing.
3Device complexity
If single parity circuit is used, then device complexity is reduced, but productivity is limited due to parity latency
Solution Approach 1:
The patent segments the parity checking function into multiple dedicated circuits (first parity circuit for odd clock cycles, second parity circuit for even clock cycles). This segmentation enables parallel processing that increases productivity and operating frequency while keeping each individual circuit relatively simple in structure.
Solution Approach 2:
The patent introduces dynamic operation by having multiple parity circuits activated at different times (alternating clock cycles) rather than all operating simultaneously. This dynamic approach increases overall productivity through parallel processing while managing device complexity through time-multiplexed activation.
Data Source
AI summary
Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.