Interleaved PFC Clock Circuit for Stable CRM Phase Shift
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Solution Overview
Problem
Interleaved Power Factor Correction (PFC) stages in power supplies face challenges in maintaining Critical Conduction Mode (CRM) operation due to unbalances or disturbances, which can cause one branch to operate in Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM, requiring complex and expensive circuitry.
Innovation Solution
A clock signal generation circuit that includes an oscillator capacitor, hysteresis comparator, and latch circuits to generate phase-shifted clock signals for each branch, ensuring a 180-degree phase shift and maintaining CRM operation efficiently, with cost-effective implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a master/slave approach is used to generate clock signals for interleaved PFC stages, then the phase relationship between sub-stages can be controlled, but the circuit complexity and cost increase due to requirements for complex and expensive circuitry to maintain CRM operation
Solution Approach 1:
The patent combines the clock signal generation for both PFC stages into a single integrated circuit that generates two clock signals with a fixed phase relationship. This merging approach eliminates the need for separate control circuits for each stage, reducing overall circuit complexity while maintaining stable phase relationships through the unified design.
Solution Approach 2:
The clock generation circuit is designed to serve multiple functions: it generates clock signals for both PFC stages, maintains the required phase relationship, and ensures CRM operation stability. This multi-functional design reduces the need for additional dedicated circuits, thereby lowering device complexity while achieving the desired stability.
2Object-generated harmful factors
If the PFC stage operates in CRM mode with varying switching frequency, then the input current waveform is improved, but a traditional oscillator cannot be used to achieve the desired phase relationship between sub-stages
Solution Approach 1:
The patent employs a dynamic clock generation approach where the switching frequency can vary while maintaining the phase relationship between clock signals. The circuit dynamically adjusts to different operating conditions, allowing CRM mode operation with improved input current waveform while still achieving the desired phase relationship through adaptive frequency control.
Solution Approach 2:
The clock generation circuit is designed to accommodate parameter changes in switching frequency while maintaining the essential phase relationship. By making the phase relationship robust to frequency variations, the circuit achieves improved input current waveform quality without requiring complex frequency-synchronized oscillators.
3Adaptability or versatility
If independent operation of both PFC branches is implemented, then each phase can operate independently in CRM mode, but the interaction to set proper phase shift becomes unpredictable and difficult to control
Solution Approach 1:
The patent segments the clock generation into two separate but synchronized clock signals, allowing each PFC branch to operate independently while receiving its own dedicated clock signal. This segmentation maintains independent operation capability while the synchronized generation ensures stable phase shift between the branches.
Solution Approach 2:
The clock generation circuit incorporates feedback mechanisms that monitor the operation of both PFC branches and adjust the clock signals accordingly. This feedback ensures that each branch can operate independently in CRM mode while the overall system maintains the proper phase shift through continuous monitoring and adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains CRM operation in interleaved PFC stages, reducing the complexity and cost of circuitry while ensuring stable operation across varying conditions, facilitating easier EMI filtering and lower input/output RMS current.
Implementation Method 1
a hysteresis comparator generates a synchronized signal in response to the oscillator capacitor voltage reaching a upper reference voltage level and a lower reference voltage level
Data Source
AI summary
A method and circuit for generating a clock signal. A power factor correction circuit has n channels operating out of phase and independently. The circuit is able to generate a clock signal for each channel according to the current cycle duration of each channel.