Interleaved Totem-Pole PFC Timing Compensation for Variable Frequency
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Solution Overview
Problem
Interleaved power factor correction circuits face challenges in maintaining optimal phase shift and efficiency at variable switching frequencies, particularly with unbalanced inductors, leading to increased losses and harmonic content, which existing solutions address inadequately using complex and costly digital signal processors or fixed phase shifts.
Innovation Solution
A method of hysteresis current control that generates compensation currents to adjust reference currents and timing differences between branches, allowing for adaptive phase shift regulation and minimizing inductor ripple current, regardless of the number of active channels and inductor balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable switching frequency operation is implemented in interleaved PFC circuits, then efficiency and adaptability are improved, but phase shift control becomes complicated and requires complex digital signal processors
Solution Approach 1:
The patent replaces complex digital signal processing mechanisms with an analog timing reference circuit that automatically generates phase-shifted control signals. The timing reference circuit uses simple analog components (resistors, capacitors, operational amplifiers) to create proportional timing references that automatically adapt to variable switching frequencies, eliminating the need for expensive DSPs or FPGAs while maintaining accurate phase control.
Solution Approach 2:
The patent changes the control parameter from fixed phase shift to proportional phase shift, where the phase shift between interleaved channels is proportional to the switching period. This allows the system to automatically adapt to variable frequency operation without requiring complex digital processing, as the timing reference circuit dynamically adjusts the phase shift based on the instantaneous switching frequency.
2Device complexity
If fixed phase shift is used in interleaved PFC circuits, then control is simplified, but performance deteriorates at variable switching frequencies and with unbalanced inductors
Solution Approach 1:
The patent implements dynamic phase shift control where the phase shift between interleaved channels is proportional to the switching period rather than being fixed. The timing reference circuit dynamically adjusts the timing references for each channel based on the instantaneous switching frequency, ensuring accurate phase control that adapts to varying operating conditions and inductor imbalances without increasing circuit complexity.
3Measurement precision
If digital signal processors are used for phase shift regulation, then control precision is improved, but cost and device complexity increase significantly
Solution Approach 1:
The patent replaces expensive digital signal processors with a cost-effective analog timing reference circuit that achieves comparable phase control precision. The timing reference circuit uses simple, inexpensive analog components to generate proportional timing references that automatically adapt to variable frequency operation, providing high-precision phase control without the high cost and complexity of DSP-based solutions.
4Ease of manufacture
If unbalanced inductors are used in interleaved PFC circuits, then component cost and size are reduced, but phase shift control becomes difficult and losses increase
Solution Approach 1:
The patent implements a feedback mechanism where the timing reference circuit continuously monitors the switching frequency and dynamically adjusts the phase shift between interleaved channels. This feedback control ensures that even with unbalanced inductors, the system maintains optimal phase relationships that minimize current ripple and reduce switching and conduction losses, allowing the use of cost-effective unbalanced inductors without performance penalty.
Data Source
AI summary
Uncompensated upper and lower reference-currents are generated for first and second branches of a high-frequency half-bridge within an interleaved-totem-pole PFC. A first control-signal for the first branch is generated from comparison between an inductor-current and uncompensated reference-currents for the first branch, a first timing-reference is generated from the first control-signal from a number of active branches, a compensated upper reference-current is generated for the second branch by adding a first compensation-current to the uncompensated upper reference-current for the second branch, a compensated lower reference-current is generated for the second branch by subtracting the first compensation-current from the uncompensated lower reference-current for the second branch, a second control-signal is generated for the second branch from the compensated reference-currents for the second branch, a first timing-difference is generated from a phase-difference between the first and second control-signals, and the first compensation-current is generated from a difference between the first timing-reference and timing-difference.