Interleaved Program-Verify Loops in Non-Volatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory systems face inefficiencies in programming operations due to the need for separate and sequential execution of program and verify stages, which can lead to increased operational delays and resource utilization.
Innovation Solution
The implementation of interleaved program-verify loops, where program and verify stages are interleaved for multiple memory cells, allowing for concurrent execution and reducing overall delay by sharing control gate biases and optimizing verify pulse sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate and sequential execution of program and verify stages is used, then data integrity is maintained, but operational delay increases
Solution Approach 1:
The memory array is divided into multiple banks that can be independently accessed. The program-verify operation is segmented across these banks, allowing different banks to execute program and verify stages in an interleaved manner. This segmentation enables parallel processing of multiple memory cells without compromising the integrity verification of each individual cell.
Solution Approach 2:
The patent implements continuous operation by eliminating idle time between program and verify stages. While one bank is in the verify stage, another bank immediately transitions to the program stage, ensuring that the memory system is continuously productive. This continuous interleaved execution maintains data integrity through proper verification while minimizing operational delay.
2Measurement precision
If separate and sequential execution of program and verify stages is used, then verification accuracy is ensured, but resource utilization decreases
Solution Approach 1:
The memory system is segmented into multiple independently controllable banks, each capable of executing program-verify loops. This segmentation allows verification operations to be distributed across multiple banks simultaneously, maintaining verification accuracy for each bank while improving overall resource utilization through parallel execution.
Solution Approach 2:
The control circuitry is designed to universally manage multiple banks with the same program-verify logic. The verify circuit can functionally serve multiple banks in sequence, making the verification resource multi-functional. This approach ensures verification accuracy is maintained while improving resource utilization by avoiding dedicated separate verification hardware for each bank.
3Productivity
If interleaved program-verify loops are implemented, then programming efficiency is enhanced, but control complexity increases
Solution Approach 1:
The control logic is segmented into bank-specific control units that manage individual banks independently. Each control unit handles the program-verify sequence for its assigned bank, simplifying the overall control architecture by breaking down the complex interleaved management into smaller, manageable segments. This segmentation enables efficient interleaved operation without requiring a monolithic complex controller.
Solution Approach 2:
The interleaved program-verify operation follows a periodic pattern where banks are systematically cycled through program and verify stages in a repeating sequence. This periodic structure simplifies control by establishing a predictable rhythm that can be managed with straightforward timing logic, reducing control complexity while maintaining high programming efficiency.
Data Source
AI summary
A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.