Interleaved Programming of Non-Volatile Memory for SSDs
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Solution Overview
Problem
The precision required for programming multi-level NAND flash memory cells leads to slower programming processes and reduced performance due to the need for precise voltage levels and the requirement to erase before programming, which complicates SSD controllers and increases costs.
Innovation Solution
Implementing an interleaved programming sequence that coarse and fine tunes neighboring word lines in a sequential process, using a sawtooth pattern of programming voltage, and employing non-volatile phase change memory with switch (PCMS) for buffering to reduce the impact of programming errors and eliminate the need for DRAM buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level programming is used to increase bits per cell, then storage density is improved, but programming time increases considerably
Solution Approach 1:
The programming process is segmented into multiple voltage levels (e.g., 16 levels for QLC), where each level represents a discrete programming stage. This segmentation allows the system to progress through intermediate states rather than attempting to reach the final state in a single step, thereby managing the complexity and time requirements of multi-level programming.
Solution Approach 2:
The method performs preliminary coarse programming to intermediate voltage levels before final fine-tuning programming. This preliminary action establishes a foundation that reduces the complexity of subsequent operations, allowing the system to achieve multi-level programming with reduced overall time by breaking the process into preparatory and completion phases.
2Reliability
If precision programming is applied to each level, then reliability is improved, but programming speed decreases
Solution Approach 1:
Programming precision is segmented into two distinct phases: coarse programming that establishes approximate voltage levels with lower precision requirements, and fine-tuning programming that achieves final precision. This segmentation allows the system to maintain reliability through precision where needed while improving overall speed by using lower precision during the more time-consuming coarse programming phase.
Solution Approach 2:
The method applies partial precision action by performing coarse programming first with relaxed precision requirements, then applying full precision only during the final fine-tuning stage. This partial application of precision to different phases of the process maintains reliability for the final result while significantly improving programming speed by avoiding excessive precision requirements throughout the entire process.
3Reliability
If complex recovery mechanisms are implemented for power loss scenarios, then data reliability is improved, but controller complexity increases
Solution Approach 1:
The system performs preliminary coarse programming to intermediate levels before fine-tuning, creating intermediate states that serve as recovery points. If power is lost during fine-tuning, the system can recover by completing the fine-tuning from the established intermediate state rather than requiring complex rollback mechanisms, thereby reducing controller complexity while maintaining reliability.
Solution Approach 2:
The programming methodology enables self-service recovery by structuring the programming process so that intermediate coarse programming states automatically serve as recovery points. The system does not require external intervention or complex recovery mechanisms because the programming structure itself provides the necessary recovery capability through its staged approach.
4Productivity
If buffering is increased to handle programming scenarios, then performance is improved, but cost increases
Solution Approach 1:
The programming process is segmented such that coarse programming can proceed with minimal buffering requirements, while fine-tuning operations are performed subsequently. This segmentation allows the system to achieve high buffering capability during coarse programming without requiring large buffers for the entire programming process, thereby improving productivity while controlling costs.
Data Source
AI summary
Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.