Time-Interleaved Sampling Circuit With Transmission-Line Clocking
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Solution Overview
Problem
In sampling circuits using a time-interleaved configuration, increasing the interleave number narrows the input band due to increased input capacitance, reducing the cutoff frequency and data rate of the input signal.
Innovation Solution
The design includes a first transmission line for input signals and a second transmission line for clock signals, both with specific propagation times, where the clock signal transmission time includes a preset sampling interval, allowing the input capacitances of sample-hold circuits to be absorbed into the transmission line constants, preventing an increase in input capacitance and maintaining a wide-band input characteristic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interleave number is increased to achieve higher sampling rates, then the sampling rate is improved, but the input capacitance increases which narrows the input band and reduces the cutoff frequency
Solution Approach 1:
A delay circuit is introduced as an intermediary component between the parallel sample-hold circuits and the input signal source. This delay circuit absorbs the cumulative input capacitance of multiple parallel circuits, preventing it from directly loading the input signal source. The delay circuit acts as a buffer that isolates the capacitance effect while maintaining signal integrity and bandwidth.
Solution Approach 2:
The sampling circuit is divided into multiple parallel sample-hold circuits operating at different time intervals (time-interleaved configuration). Each circuit operates independently at a lower clock frequency, but their combined output achieves a higher effective sampling rate. This segmentation allows the system to achieve high productivity without each individual circuit needing to handle the full capacitance load.
2Productivity
If the interleave number is increased to achieve higher sampling rates, then the sampling rate is improved, but the cutoff frequency is reduced
Solution Approach 1:
The delay circuit serves as a mediator that prevents the cumulative input capacitance from directly affecting the input signal source. By placing this intermediary component in the signal path, the circuit isolates the source from the capacitive loading effect, thereby maintaining the cutoff frequency while still achieving higher sampling rates through time-interleaved operation.
3Productivity
If the clock frequency is increased to achieve higher sampling rates, then the sampling rate is improved, but the design requirements for clock generation circuits and sampling circuits become more stringent
Solution Approach 1:
The high sampling rate requirement is segmented across multiple parallel circuits operating at lower, more manageable clock frequencies. Each sample-hold circuit uses a clock frequency that is 1/N of the desired overall sampling rate, where N is the interleave number. This segmentation makes the clock generation and distribution much simpler while achieving the same effective sampling rate through time-interleaved operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains a wide-band input characteristic and prevents the reduction in cutoff frequency even with increased interleave numbers, ensuring high data rates without the need for elevated clock frequencies.
Implementation Method 1
a first transmission line that transmits an input signal input from one end to the other end; the first transmission line transmits the input signal at a first propagation time for each of the line distances
Implementation Method 2
a second transmission line that transmits a clock signal input from one end to the other end; the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time
Implementation Method 3
The input signal is held by capacitive elements Cs of the sample-hold circuits SH at timing at which the switches SW are switched ON by the clock signal ck, and their holding voltages are output as sampling voltages Vs(i)
Data Source
AI summary
A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.