Time-Interleaved Sampling Circuit With Power-Gated Input Buffers
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Solution Overview
Problem
Existing signal sampling circuits face challenges in achieving high bandwidth and low power consumption, particularly when sampling high-frequency input signals.
Innovation Solution
The proposed signal sampling circuitry employs a plurality of sampling units configured for time-interleaved sampling, each equipped with an input buffer and power gating switches to manage power consumption. This design ensures high bandwidth by minimizing the impact of input buffer resistance and capacitance and reduces power consumption by powering down the input buffer when not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sampling unit is used for high-speed sampling, then the circuit complexity is low, but the sampling bandwidth is insufficient for high-frequency signals
Solution Approach 1:
The sampling circuit is divided into multiple parallel sampling units (e.g., 2N units) that operate simultaneously with time-interleaved sampling. Each unit handles a portion of the sampling task, collectively achieving high-speed sampling of high-frequency signals while maintaining manageable individual unit complexity.
2Speed
If multiple sampling units are used for time-interleaved sampling to achieve high bandwidth, then the sampling speed increases, but the power consumption increases
Solution Approach 1:
The input buffers in parallel sampling units are selectively activated and deactivated in a periodic manner based on the sampling phase requirements. During time-interleaved sampling, only the necessary buffers are powered on, while others are powered off, reducing overall power consumption while maintaining high sampling speed.
3Device complexity
If a single large input buffer is used to drive multiple sampling units, then the device complexity is low, but the buffer resistance and capacitance degrade the sampling bandwidth
Solution Approach 1:
Instead of using a single large input buffer, the design employs multiple smaller input buffers (one per sampling unit or selectively activated). Each buffer drives a limited number of sampling units, minimizing the total capacitive load and resistance impact on sampling bandwidth while maintaining manageable device complexity.
Solution Approach 2:
The input buffers are dynamically controlled through power gating, where buffers are activated only when needed for specific sampling phases. This dynamic activation reduces the effective capacitive load on the signal distribution network, improving sampling bandwidth while keeping the buffer configuration manageable.
4Speed
If input buffers are continuously powered to maintain high bandwidth readiness, then the sampling bandwidth is maintained, but the power consumption increases
Solution Approach 1:
Input buffers are powered on only during the specific time intervals when they are needed for sampling operations, and powered off during idle periods. This periodic power management maintains sampling bandwidth readiness when needed while significantly reducing average power consumption.
Solution Approach 2:
The power state of input buffers is dynamically adjusted based on real-time sampling requirements. Buffers transition between active and inactive states according to the sampling phase, ensuring high bandwidth readiness during active periods while minimizing power consumption during inactive periods.
Data Source
AI summary
A signal sampling circuitry comprises: a plurality of sampling units receiving an input signal for time-interleaved sampling, each sampling unit comprising: a sampling capacitor having a first plate connected to an output of the sampling unit; a first plate switch between the first plate and a first reference voltage, a second plate switch between a second plate of the sampling capacitor and a second reference voltage; an input buffer for outputting a buffered input signal to the second plate; wherein the input buffer is connected to at least one power gating switch for powering down the input buffer.