Interleaved SAR ADC Clocking With Conversion Suspension for Noise Control
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Solution Overview
Problem
Interleaving control in SAR ADC circuit architectures faces challenges with noise interference from one ADC to another, leading to differential non-linearity issues, with conventional solutions either increasing cost, power consumption, or conflicting with speed goals.
Innovation Solution
An ADC device with a conversion suspension function, utilizing an interleaved clock controller to generate distinct clock signals for multiple ADCs, allowing one ADC to suspend conversion operations when another is sampling, thereby minimizing noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interleaving control is used to increase operation speed, then productivity is improved, but noise interference between ADCs worsens measurement precision
Solution Approach 1:
The patent applies dynamics by making the conversion operation state changeable - the ADC can dynamically switch between performing conversion and suspending conversion based on real-time noise conditions. The control unit monitors whether another ADC is in sampling state and dynamically adjusts the conversion operation accordingly, allowing the system to adapt its behavior to maintain precision while preserving interleaving speed benefits.
2Measurement precision
If conventional methods are used to reduce noise interference, then measurement precision is improved, but device complexity or cost increases
Solution Approach 1:
The patent applies self-service by enabling the ADC to monitor and control its own conversion operations based on internal state information. The control unit uses the existing sampling state information of other ADCs to make autonomous decisions about whether to suspend conversion, eliminating the need for external noise filtering hardware or complex isolation circuits while maintaining measurement precision.
3Productivity
If conversion operation continues without suspension, then productivity is improved, but noise interference worsens measurement precision
Solution Approach 1:
The patent applies feedback by using the sampling state information of one ADC as feedback to control the conversion operation of another ADC. The control unit receives real-time state information and adjusts the conversion operation accordingly - when sampling noise is detected, conversion is suspended; when noise is absent, conversion proceeds. This closed-loop control maintains precision without significantly impacting overall productivity.
Data Source
AI summary
An analog-to-digital converter (ADC) device equipped with a conversion suspension function and an associated operation method thereof are provided. The ADC device includes: an interleaved clock controller, arranged to generate a first clock signal and a second clock signal according to a master clock signal; and a multi-ADC circuit, coupled to the interleaved clock controller, arranged to perform analog-to-digital conversion. The multi-ADC circuit includes a first ADC and a second ADC, wherein the first ADC performs sampling and conversion operations according to the first clock signal, and the second ADC performs sampling and conversion operations according to the second clock signal. Based on the timing control of the first clock signal and the second clock signal, when any ADC of the first ADC and the second ADC is performing a sampling operation, the other ADC of the first ADC and the second ADC suspends conversion.