Time-Interleaved Noise-Shaping SAR ADC for Low-Power Speed
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Solution Overview
Problem
Noise-shaping successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in achieving high speed at low power due to the limitations of shortening operational phases such as acquisition, bit trial, and residue charge transfer phases, which result in higher power consumption.
Innovation Solution
The implementation of time-interleaved signal acquisition with a shared noise-shaping circuit using multiple digital-to-analog converter (DAC) circuits, allowing for increased time allocation to these phases and reducing power consumption by controlling the timing between DACs and the noise-shaping circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the acquisition phase, bit trial phase, and residue charge transfer phase are shortened to achieve high speed conversion, then the conversion speed is improved, but the power consumption increases
Solution Approach 1:
The patent divides the ADC operation into multiple phases (acquisition phase, bit trial phase, residue charge transfer phase) and processes multiple samples through these phases in an interleaved manner. By segmenting the conversion process and reusing the noise-shaping circuit across different samples and phases, the circuit can operate more efficiently with lower power consumption while maintaining high conversion speed.
2Duration of action of moving object
If multiple DAC circuits are used with time-interleaved operation, then the time available for acquisition, bit-trial, and residue charge transfer phases is increased, but the device complexity increases
Solution Approach 1:
The patent merges multiple DAC circuits into a time-interleaved architecture where they share a common noise-shaping circuit. This combining approach allows the system to process multiple samples simultaneously through different DACs while sharing the more complex noise-shaping functionality, thereby increasing the effective time available for conversion phases without proportionally increasing overall circuit complexity.
Solution Approach 2:
The noise-shaping circuit is designed to serve multiple functions and multiple DAC circuits simultaneously. It processes residue charges from different DACs during different phases (acquisition, bit trial, residue charge transfer), making it a universal component that handles multiple tasks. This multi-functionality reduces the need for separate dedicated circuits for each DAC, thereby managing complexity while extending operational time.
3Measurement precision
If the acquisition phase time is increased to improve signal accuracy, then the measurement precision is improved, but the conversion speed decreases
Solution Approach 1:
The patent implements continuous operation where multiple DAC circuits work in parallel through time-interleaved phases. While one DAC is in acquisition phase, another is in bit trial phase, and a third is in residue charge transfer phase. This continuity ensures that signal acquisition accuracy is maintained through adequate phase durations while the overall conversion speed remains high due to parallel processing and seamless phase transitions.
Data Source
AI summary
Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.