Interleaved Signal Circuit With Controllable Delay Output
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Solution Overview
Problem
Existing methods for generating equidistant stagger signals face issues with controllability of delay between signals, leading to increased circuit area and power consumption, especially when using asynchronous signals, and fixed integer multiples of clock periods when using synchronous signals.
Innovation Solution
A stagger signal generation circuit that includes a stagger pulse generation circuit and a delay signal output circuit, generating stagger pulse signals from inverted control signals and adjusting delays through a series of signal output circuits, allowing flexible control of delay intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If asynchronous signals are used to generate equidistant stagger signals, then the controllability of delay between signals is improved, but the area of the formed circuit layout and the power consumption of the circuit are significantly increased
Solution Approach 1:
The patent combines the delay control function with the signal generation function by using a single synchronous clock signal to generate multiple stagger signals with different delays. The delay control is achieved through selecting different clock cycles rather than using separate asynchronous signal paths, thereby merging multiple functions into one circuit structure.
Solution Approach 2:
The patent creates a universal signal generation circuit that can produce multiple equidistant stagger signals with different delay values by controlling the clock cycle selection. This multi-functional circuit replaces multiple dedicated delay circuits, reducing overall circuit area while maintaining flexible delay control capability.
2Ease of operation
If asynchronous signals are used to generate equidistant stagger signals, then the controllability of delay between signals is improved, but the power consumption of the circuit is significantly increased
Solution Approach 1:
The patent merges the delay control mechanism into the synchronous clock distribution network, eliminating the need for separate asynchronous delay circuits. This integration reduces the total number of active circuit elements and their associated power consumption while preserving delay controllability through clock cycle selection.
Solution Approach 2:
The universal clock distribution circuit serves multiple functions: generating equidistant stagger signals, controlling delay intervals, and adapting to different timing requirements. This multi-functionality reduces the need for multiple dedicated circuits, thereby lowering overall power consumption.
3Area of stationary object
If synchronous signals are used to generate equidistant stagger signals, then the circuit area and power consumption are reduced, but the delay between equidistant stagger signals is necessarily an integer multiple of a clock period, resulting in poor controllability
Solution Approach 1:
The patent introduces dynamic clock cycle selection capability into the synchronous signal generation circuit. By allowing the clock cycle to be dynamically adjusted based on control signals, the circuit can achieve non-integer multiple delays while maintaining the area efficiency of synchronous design. The dynamic adaptation enables fine-grained delay control without sacrificing circuit compactness.
Data Source
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AI summary
A stagger signal generation circuit is provided. The stagger signal generation circuit includes: a stagger pulse generation circuit, configured to generate a first pulse signal according to a first control signal and generate a second pulse signal according to a second control signal, the first control signal and the second control signal being inverted signals, and the first pulse signal and the second pulse signal being stagger pulse signals; and a delay signal output circuit including G signal output circuits, G being an integer greater than or equal to 2. Each non-first-stage signal output circuits receives a delay output signal outputted by a respective previous-stage signal output circuit as an input signal of a current-stage signal output circuit, and a first-stage signal output circuit receives an initial input signal as an input signal of the first-stage signal output circuit. The embodiments of this application generate a first pulse signal and a second pulse signal with adjustable periods, and generate a delay signal with a controllable delay according to the first pulse signal and the second pulse signal, and an area of a circuit layout is small, and the power consumption of the circuit is low.