Time-Interleaved Signal Acquisition Circuit for Full-Bandwidth Triggering
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Solution Overview
Problem
Current measurement systems, such as oscilloscopes and spectrum analyzers, face limitations in processing high bandwidth input signals due to under-sampling, which restricts the ability to apply complex trigger scenarios and discards signal edges, especially when the data rate exceeds the sampling rate.
Innovation Solution
A signal acquisition circuit with multiple acquisition units operating in parallel, where at least two units are time-interleaved and share a common trigger unit, allowing for real-time processing of high bandwidth signals without bandwidth limitations, enabling complex trigger scenarios and maintaining all signal edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple acquisition units operate in parallel with each having its own trigger processor, then the sampling rate increases to handle high bandwidth signals, but the trigger processing complexity increases and the ability to consider the entire bandwidth for triggering is lost
Solution Approach 1:
The patent merges the trigger processing functionality into a single centralized trigger processor that receives inputs from multiple acquisition units. This consolidation reduces the number of trigger processors from multiple (one per acquisition unit) to a single unit, thereby reducing device complexity while maintaining the ability to handle high bandwidth signals through parallel acquisition units.
Solution Approach 2:
The centralized trigger processor is designed to handle triggering for the entire bandwidth by receiving and processing signals from all acquisition units. This universal trigger processor can consider the entire bandwidth for triggering decisions, unlike individual trigger processors that could only consider their respective sub-channels.
2Ease of operation
If each sub-channel has its own trigger processor processing only its interleaved input signal, then the trigger detection is simplified for each channel, but complex trigger scenarios cannot be applied across the entire bandwidth
Solution Approach 1:
The centralized trigger processor is designed to handle multiple input signals from different acquisition units simultaneously. It can apply complex trigger scenarios that consider the entire bandwidth by processing and comparing signals from all channels, thereby providing versatility for complex trigger scenarios while maintaining ease of operation through a unified processing approach.
3Productivity
If the data rate of the input signal exceeds the sampling rate of a single acquisition unit, then real-time processing requires multiple parallel acquisition units, but this increases the number of components and system complexity
Solution Approach 1:
The patent combines multiple acquisition units into a parallel processing architecture where they share a common trigger processor. This merging approach allows real-time processing of high data rate signals by distributing the sampling across multiple units while reducing overall system complexity through shared resources, particularly the centralized trigger processor.
Data Source
AI summary
A signal acquisition circuit for acquiring data of an input signal comprising at least n acquisition units, wherein n is integer greater than one, the n acquisition units comprising k inputs, wherein k is integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition units run time interleaved, and at least one trigger unit, wherein the number 1 of the at least one trigger unit is integer and wherein 1 is smaller than k. Further, a single-housed device as well as a method of acquiring data of an input signal are described.