Interleaved Stripe Routing Structure for IC Noise Reduction
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Solution Overview
Problem
Conventional routing structures for re-distribution layers (RDL) in integrated circuits focus primarily on providing power to core circuits rather than effectively reducing noise, which is essential for high-density, high-speed signal transmission in modern multimedia applications.
Innovation Solution
A routing structure for RDL comprising power routes, first and second stripes arranged in specific directions, and ground routes, where the first and second stripes are interleaved without intersecting, enhancing the de-coupling capacitor effect to filter noise. The structure includes power and ground routes with bumps and line segments, and the stripes are connected to these elements, forming acute angles to maximize noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional routing structure is used to provide power to core circuit, then power supply function is achieved, but noise reduction capability is insufficient
Solution Approach 1:
The routing structure is segmented into multiple functional components: power routes with first bumps and first line segments, ground routes with second bumps and second line segments, and interleaved first stripes and second stripes. This segmentation allows each component to serve specific functions (power delivery, ground reference, noise filtering) while collectively achieving both power supply and noise reduction without excessive complexity
Solution Approach 2:
The first stripes and second stripes act as intermediary elements between the power routes and ground routes. These stripes are connected to respective bumps and line segments, creating intermediate coupling points that enhance the de-coupling capacitor effect and filter noise while maintaining the overall routing structure's power delivery function
2Adaptability or versatility
If bumps are arranged in peripheral type for wire bonding, then wire bonding connection is achieved, but flip-chip array type connection is not achieved
Solution Approach 1:
The routing structure is designed with universal adaptability to support multiple packaging techniques. The interleaved stripe configuration and distributed bump arrangement (both peripheral first bumps and array-style second bumps) allow the same RDL structure to work with both wire bonding and flip-chip packaging methods, eliminating the need for separate designs for different package types
Solution Approach 2:
The invention transitions from traditional two-dimensional peripheral bump arrangements to a multi-dimensional configuration where bumps are distributed across the chip surface in both peripheral and array patterns. The interleaved stripes extend in directions forming acute angles with power and ground routes, creating a three-dimensional routing topology that accommodates both packaging approaches
Data Source
AI summary
A routing structure of an RDL of a chip is provided. The routing structure comprises a power route, a plurality of first stripes, a ground route, and a plurality of second stripes. The power route is arranged in a first direction and comprises a plurality of first bumps and a plurality of first line segments. Each of the first line segments connects adjacent first bumps. The first stripes are arranged in a second direction and connected to the power route. The ground route is disposed at one side of the power route in a third direction, and comprises a plurality of second bumps and a plurality of second line segments. Each of the second line segments connects adjacent second bumps. The second stripes, are arranged in a forth direction and connected to the ground route. The first stripes and the second stripes are interleaved without intersecting one another.