Interleaved Super-Plane-Block Writes for SSD Write Amplification
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Solution Overview
Problem
Solid state drives (SSDs) face performance degradation and increased write amplification due to the block erase nature of NAND operation, especially when multiple data streams are written to the same pool of blocks, leading to random workloads and inefficiencies in garbage collection.
Innovation Solution
The implementation of super-plane-blocks spanning different planes of user data dies and/or XOR dies, allowing simultaneous writing of multiple data streams without die contention, reducing the erasable unit size, and simplifying XOR operations and data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple data streams are written to the same pool of blocks or superblock, then the sequential workloads change to random workloads, but this causes performance degradation and increased write amplification
Solution Approach 1:
The patent divides the NAND memory structure into multiple independent planes within superblocks, allowing each plane to handle separate data streams independently. This segmentation prevents multiple sequential writes from interfering with each other, maintaining performance while supporting multiple data streams simultaneously.
Solution Approach 2:
The patent introduces a plane dimension to the traditional block structure, organizing data streams across multiple planes rather than sequentially within a single plane. This dimensional expansion allows parallel processing of multiple data streams, converting what would be sequential random operations into concurrent plane-level operations.
2Quantity of substance
If multiple data streams are written to the same pool of blocks, then more physical capacity is consumed, but this increases write amplification factor
Solution Approach 1:
By segmenting the memory into plane-specific superblocks, the patent enables independent management of each data stream. Valid data in one plane can be preserved while invalid data in another plane is erased, avoiding the need to erase entire superblocks and reducing write amplification.
Solution Approach 2:
The patent applies different operations to different planes based on their specific data validity status. Each plane can be erased or preserved independently according to its local data state, optimizing the use of physical capacity while minimizing unnecessary write operations.
3Productivity
If the erasable unit size is reduced to improve garbage collection efficiency, then more management overhead is required
Solution Approach 1:
The patent segments the erasable unit from the traditional superblock level down to the plane level. This creates smaller, more manageable erasable units that can be processed independently, improving garbage collection efficiency without requiring complex cross-plane coordination.
Solution Approach 2:
The patent performs preliminary organization of data streams into plane-specific superblocks during the write phase. This preliminary action ensures that future garbage collection operations can work with pre-organized, plane-isolated data structures, reducing the complexity of real-time management.
Data Source
AI summary
In one embodiment, a solid state device includes a controller and a non-volatile memory. The non-volatile memory includes a plurality of dies. Each die includes a plurality of planes. A first super-plane-block is structured from a first plane of the plurality of dies. A second super-plane-block is structured from a second plane of the plurality of dies. A plurality of memory operation instructions that, when executed by the controller, cause the controller to receive a first data stream, write the first data stream to the first super-plane-block, receive a second data stream, and write the second data stream to the second super-plane-block.