Interleaved IC Tap Cell Layout for Lower Well Tap Resistance
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Solution Overview
Problem
The placement of TAP cells in integrated circuits (ICs) during manufacturing faces challenges such as process bottlenecks due to reduced lithography critical dimension and mixed channel effects, particularly at advanced nodes, which affect latch-up immunity and well tap resistance.
Innovation Solution
TAP cells are arranged in an interleaving manner in two transverse directions with a double cell height, alternating rows and columns, and configured to collect body currents from wider areas, reducing well tap resistance and improving latch-up immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TAP cells are placed using conventional methods, then manufacturing process is simpler, but latch-up immunity is poor and well tap resistance is high
Solution Approach 1:
The patent segments TAP cells into different types (first TAP cells and second TAP cells) and arranges them in separate alternating rows. This segmentation allows each type to be optimized for specific functions while maintaining overall latch-up immunity, resolving the contradiction between reliability improvement and manufacturing complexity by organizing complexity in a systematic, rule-based manner.
Solution Approach 2:
The patent introduces a new dimensional arrangement by placing TAP cells in alternating rows rather than conventional single-row or grid patterns. This alternating row configuration adds a spatial dimension to TAP cell placement, improving latch-up immunity through better current collection geometry while maintaining manufacturability through clear placement rules.
2Reliability
If TAP cells are arranged to collect body currents from wider areas, then well tap resistance is reduced, but chip area is increased
Solution Approach 1:
The patent merges first TAP cells and second TAP cells into a unified alternating row structure that collectively covers wider areas for body current collection. By combining different TAP cell types in an interleaved pattern, the design achieves extended current collection coverage and reduced well tap resistance without requiring proportional increases in total chip area, as the structure shares space efficiently.
Solution Approach 2:
The patent applies local quality by positioning different types of TAP cells in specific alternating rows, where each type can be optimized for local current collection needs. This localized optimization allows wider area coverage for current collection in regions where it is most needed, while maintaining compactness in other areas, thus reducing well tap resistance without uniformly increasing chip area.
3Manufacturing precision
If lithography critical dimension is reduced for advanced nodes, then manufacturing precision is improved, but process bottlenecks increase and mixed channel effects worsen
Solution Approach 1:
The patent segments the TAP cell structure into alternating rows of different types, which helps separate mixed channel effects into distinct spatial zones. This segmentation reduces the impact of mixed channel effects at advanced nodes with reduced lithography critical dimensions, allowing manufacturing to proceed without severe process bottlenecks while maintaining high precision requirements.
Data Source
AI summary
An integrated circuit (IC) device includes a plurality of first taps arranged in a plurality of first columns and a plurality of first rows, and a plurality of second taps arranged in a plurality of second columns and a plurality of second rows. The plurality of second taps has a type different from the plurality of first taps. Each first tap of the plurality of first taps extends continuously across multiple rows of first active regions. Each second tap of the plurality of second taps extends continuously across multiple rows of second active regions. The second active regions have a type different from the first active regions. Along a column direction of the plurality of first columns and the plurality of second columns, no first tap among the plurality of first taps overlaps any second tap among the plurality of second taps.