Interleaved Video Data Storage for H.264 Block Access
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Solution Overview
Problem
Conventional video storage methods are inefficient in accessing and processing rectangular areas of images, particularly in modern memory devices, due to limitations in address loading and data transfer, which affects video source coding standards like H.264 that require small, off-grid rectangular regions.
Innovation Solution
The method involves interleaving data access between two DRAM devices using a memory controller to reduce address loading and optimize data transfer, allowing for efficient reading of small rectangular areas by distributing data evenly between the devices and using a checkerboard pattern for tile allocation, thereby simplifying on-chip hardware and improving bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If video data is stored in conventional raster format, then the storage structure is simple, but the number of pages accessed for processing 9x9 blocks increases significantly
Solution Approach 1:
The image is divided into 32x32 pixel tiles, and each tile is further segmented into 4 sub-tiles arranged in a 2x2 grid. This segmentation allows 9x9 blocks to be distributed across fewer pages, reducing the number of page accesses required during processing while maintaining a structured storage layout.
Solution Approach 2:
The patent introduces a new dimensional organization by arranging tile data in an interleaved pattern across multiple memory pages. Instead of sequential row-major ordering, data is distributed across pages in a pattern that aligns with the spatial locality requirements of 9x9 block processing, effectively adding a memory-access dimension to the storage organization.
2Productivity
If data is stored in tiled format to reduce page accesses, then data access efficiency improves, but memory controller complexity increases
Solution Approach 1:
The patent employs asymmetric addressing where even and odd numbered sub-tiles within each tile are stored in different memory banks. This asymmetric arrangement allows the memory controller to service multiple sub-tiles in parallel by distributing them across independent memory banks, reducing the complexity burden while maintaining high access efficiency.
Solution Approach 2:
The interleaved tile storage pattern is designed to be self-service friendly for the memory controller. By naturally distributing consecutive sub-tiles across different banks, the system enables the memory controller to automatically service multiple tiles without requiring complex arbitration or scheduling logic, thus reducing controller complexity.
3Ease of manufacture
If conventional memory access methods are used, then hardware implementation is straightforward, but bandwidth utilization is inefficient for video processing
Solution Approach 1:
The patent performs preliminary organization of video data into interleaved tiles during the storage phase. This preliminary action ensures that when 9x9 blocks need to be processed, the required data is already positioned in an optimal access pattern across memory pages, eliminating the need for complex runtime reorganization and enabling efficient bandwidth utilization with straightforward hardware.
Solution Approach 2:
The patent changes the fundamental storage parameter from sequential raster ordering to interleaved tile-based ordering. This parameter change transforms the data layout to match the access patterns required by video processing algorithms, enabling efficient bandwidth utilization while keeping the hardware implementation relatively simple through regular, predictable access patterns.
Data Source
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AI summary
A method for reading atoms positioned within a memory- having a first memory portion and a second memory portions, comprising the steps of (a) positioning the atoms having memory addresses across the memory, (b) defining a strip across a portion of the atoms, (c) designating a first atom within the strip, (d) locating one or more second atoms to be paired with the first atom, (e) determining whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (f) reading the legitimate pair from the first memory portion and the second memory portion.