Digital Pixel Word-Line Layout for Noise-Resistant Image Sensing
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Solution Overview
Problem
Conventional image sensors using analog pixels face challenges in processing high-resolution image signals due to noise and coupling issues during the conversion of analog signals to digital signals.
Innovation Solution
The implementation of digital pixels with photo detectors and memory cells that output digital signals directly, connected through a network of bit lines and word lines, allowing for reduced noise susceptibility and efficient image processing at the pixel level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog pixels are used to detect light signals, then the image sensor can capture optical information, but noise and coupling issues occur during signal transmission reducing image quality
Solution Approach 1:
The patent segments the pixel array into multiple banks, where each bank contains a subset of pixels with dedicated memory cells. This segmentation isolates signal paths, reducing coupling between adjacent pixels and minimizing noise interference during signal transmission while maintaining high image quality.
Solution Approach 2:
The patent introduces memory cells as intermediary elements between the photo detectors and readout circuits. These memory cells temporarily store signals from adjacent pixels, acting as buffers that prevent direct coupling and reduce noise during signal transmission, thereby improving image quality.
2Reliability
If digital pixels with memory cells are used for direct digital signal processing, then noise and coupling issues are reduced, but the device complexity increases
Solution Approach 1:
The patent designs memory cells with dual functionality: they serve as temporary storage elements for pixel signals and as part of the readout circuitry. This multi-functionality reduces the need for separate dedicated components, thereby improving signal transmission reliability while minimizing the increase in device complexity.
Solution Approach 2:
The patent merges the memory cell array with the pixel structure, integrating storage functionality directly into the pixel circuit. By combining multiple functions (detection, storage, and readout) into a unified structure, the patent achieves reliable digital signal processing without proportionally increasing overall device complexity.
3Productivity
If multiple memory cells are connected with bit lines and word lines for digital signal storage, then high-speed image processing is enabled, but the area occupied by memory structures increases
Solution Approach 1:
The patent transitions from a one-dimensional linear memory structure to a two-dimensional array configuration for memory cells, organized with bit lines and word lines. This dimensional change enables parallel access to multiple memory cells simultaneously, achieving high-speed image processing while optimizing the area utilization of the memory structure.
Solution Approach 2:
The patent implements preliminary storage of pixel signals in memory cells before readout operations. By pre-storing signals in a structured array format with organized bit and word lines, the system enables rapid sequential access and processing, achieving high productivity without requiring excessive memory area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed image signal processing with reduced noise and coupling, improving the quality of final images by generating and processing digital signals at the pixel level.
Implementation Method 1
a first photo detector and first memory cells configured to store a first digital signal corresponding to a first detection signal from the first photo detector
Data Source
AI summary
An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.