Interleaved XOR Parity Layout for Multi-Plane NAND Error Recovery
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Solution Overview
Problem
Existing memory systems using flash memory, such as NAND, are prone to read errors due to the failure of error correcting codes, especially in cases of dual-plane or multi-plane errors, which current XOR-based recovery schemes cannot effectively correct without increasing data redundancy and reducing performance.
Innovation Solution
Implementing a memory system with two parity pages per stripe, where data pages and parity pages are stored across multiple memory dies with each die having multiple planes, and cyclically interleaving the data and parity pages to enable correction of dual-plane or multi-plane errors while maintaining low data redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional XOR-based recovery schemes are used, then single-plane errors can be corrected, but dual-plane or multi-plane errors cannot be corrected
Solution Approach 1:
The invention divides the stripe into multiple segments by creating multiple parity pages (first parity page and second parity page) instead of using a single parity page. This segmentation allows different parity pages to protect against different types of errors, enabling the system to correct both single-plane errors and dual-plane errors by distributing the protection coverage across multiple segments.
2Reliability
If data redundancy is increased to correct multi-plane errors, then error correction capability improves, but write amplification increases and random write performance deteriorates
Solution Approach 1:
The invention applies different protection qualities to different parts of the data structure by creating specialized parity pages for different error types. The first parity page provides protection for single-plane errors while the second parity page provides protection for dual-plane errors. This local quality approach allows the system to provide targeted protection where needed without uniformly increasing redundancy across all data, thereby maintaining better write performance.
Data Source
AI summary
Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.