Interleaver Address Generation That Bypasses Pruned Turbo Decoder Addresses
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Solution Overview
Problem
Current interleaver address generators in 3G/UMTS systems face inefficiencies due to address pruning, leading to slower decoding, increased power consumption, and higher complexity, as they require additional hardware and memory to ensure continuous valid address generation, especially when dealing with varying block sizes and global roaming between different standards.
Innovation Solution
The interleaver address generator employs a pruning avoidance buffer and a training sequencer to pre-emptively identify and bypass invalid addresses, allowing for a single engine to produce a continuous stream of valid addresses, reducing the need for dual engines and memory, and optimizing the interleaver address generation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address pruning is used to ensure continuous valid address generation, then decoding reliability is improved, but device complexity increases due to additional hardware and memory requirements
Solution Approach 1:
The patent implements a training phase before normal decoding operation where the interleaver address generator pre-computes and stores the valid address pattern for the current block size. This preliminary action eliminates the need for complex runtime address pruning logic, as the valid address sequence is prepared in advance and stored in a buffer, thereby reducing device complexity while maintaining decoding reliability.
2Productivity
If dual engines are used to generate valid addresses, then productivity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent uses a training phase to pre-compute the valid address pattern and store it in a buffer before normal decoding operation. During decoding, this pre-computed address pattern is used directly, eliminating the need for dual engines. This preliminary computation approach maintains high decoding speed while significantly reducing device complexity compared to dual-engine solutions.
Solution Approach 2:
The patent creates a copy of the valid address pattern computed during training and stores it in a buffer for reuse during normal decoding operation. This copying approach allows the system to use a single engine for address generation while maintaining high productivity, as the pre-computed address pattern is reused rather than requiring multiple engines to generate addresses in real-time.
3Ease of operation
If lookup tables are used to store address patterns, then ease of operation is improved, but memory requirements increase
Solution Approach 1:
The patent computes and stores the valid address pattern in a buffer during a training phase before normal decoding operation. This preliminary computation approach stores only the necessary address pattern for the current block size rather than maintaining large lookup tables for all possible block sizes, thereby reducing memory requirements while maintaining ease of operation through pre-computed address sequences.
Data Source
AI summary
An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.