Parallel Address Queue Arbitration in High-Throughput Interleavers
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Solution Overview
Problem
Existing interleavers and address generators for wireless communication systems lack high throughput while being flexible for all interleave patterns, including complicated ones, due to inefficiencies in address generation processes.
Innovation Solution
A multiple-processor-based interleaver system that generates read-addresses in parallel, uses address queues to manage these addresses, and employs an arbiter to select non-empty queues for output, reducing wait cycles and increasing throughput by providing a read-address whenever possible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a typical processor (CPU or microprocessor) is used to generate addresses flexibly, then adaptability to various interleave patterns is improved, but throughput deteriorates due to sequential instruction execution
Solution Approach 1:
The address generator is divided into multiple independent address generation units (AGUs), each capable of generating addresses independently in parallel. This segmentation allows simultaneous generation of multiple addresses, dramatically increasing throughput while maintaining flexibility through configurable AGU operations
Solution Approach 2:
Multiple address generation units are merged into a unified address generation system that can operate in different modes (sequential, parallel, interleaved). The merged system combines the flexibility of software-controlled address generation with the speed of hardware parallel execution
2Productivity
If multiple address queues are used to store read-addresses from multiple processors, then throughput is improved by reducing wait cycles, but device complexity increases
Solution Approach 1:
An arbiter is introduced as an intermediary component that manages multiple address queues and selects addresses for output. The arbiter simplifies queue management by implementing a systematic selection algorithm that monitors queue depths and selects from non-empty queues, reducing the complexity burden on the overall system
Solution Approach 2:
The address queue system is designed to be dynamic, with the arbiter adaptively selecting from different queues based on their current state. The system dynamically balances the load across multiple queues and processors, optimizing throughput without requiring complex static configuration
3Productivity
If parallel address generation is implemented using multiple processors, then throughput is improved, but the number of address queues and arbitration logic increases complexity
Solution Approach 1:
The address generation units are designed as universal, multi-functional components that can execute different address generation algorithms and patterns. Each AGU can be configured to handle various interleave patterns through programmable control logic, reducing the need for dedicated hardware for each pattern and thereby reducing overall system complexity
Data Source
AI summary
An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an address queue among the address queues that is not empty based on status of each address queue; decoding the address from the selected address queue to a read-address and a bit-address; extracting a read-word from data to be interleaved based on the read-address; selecting a write-bit from the read-word based on the bit-address; arbitrating an individual write-bit to one of the write-words based on an address queue ID of the selected address queue; and generating write-addresses for respective write-words.