Interleaver-Based Error Correction Coding for Variable Transmission Speeds
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Solution Overview
Problem
Existing error correction systems in communication devices face challenges in efficiently changing transmission speeds without increasing circuit scale and cost, particularly when transitioning from 100 Gigabit/sec to 200 Gigabit/sec, as they require parallel operation of multiple error correction encoders, leading to larger circuit sizes and higher costs.
Innovation Solution
The proposed solution involves an encoder and decoder device that operate in standard and K-times speed modes, utilizing an interleaver circuit to rearrange bit sequences in a way that reduces storage capacity requirements, allowing for speed changes without increasing circuit scale by generating coded sequences based on different column intervals in standard and high-speed modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple error correction encoders are mounted in parallel to increase execution speed, then the error-correction coding speed is improved, but the circuit scale and device cost increase
Solution Approach 1:
The patent implements dynamic operation modes where a single encoder can operate at different speeds by switching between standard speed mode and high speed mode. The encoder dynamically adjusts its processing rate based on whether one or multiple data sequences are input, eliminating the need for multiple fixed-speed encoder units while achieving variable coding speeds.
Solution Approach 2:
The single error correction encoder is designed to perform multiple functions: it can process one data sequence at standard speed or multiple data sequences at high speed. This multi-functional design allows the same hardware resource to serve different throughput requirements, replacing the need for multiple specialized encoder units.
2Productivity
If multiple error correction encoders are mounted in parallel to increase execution speed, then the error-correction coding speed is improved, but the device cost increases
Solution Approach 1:
The encoder dynamically adjusts its operation between standard speed and high speed modes based on the number of input data sequences. This dynamic capability allows a single encoder unit to replace multiple fixed-speed units, reducing device cost while maintaining the ability to scale coding speed according to traffic demand.
3Adaptability or versatility
If the circuit is designed to support variable execution speeds, then the adaptability to different transmission speeds is improved, but the circuit scale increases
Solution Approach 1:
The encoder is designed with dynamic operation modes that allow it to adapt to different transmission speeds. By switching between standard speed mode (processing one data sequence) and high speed mode (processing multiple data sequences in parallel), the same circuit achieves variable speeds without requiring multiple dedicated circuits for each speed level.
Solution Approach 2:
The single encoder circuit is designed to universally handle both standard speed and high speed operations. The same hardware resources perform different functions depending on the operation mode, providing speed adaptability without increasing circuit scale through multiple specialized units.
Data Source
AI summary
An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (321, 322) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL1, IL2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (321, 322) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL1) or the two series of yet-to-be-coded bit sequences (IL1, IL2).